Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
2000-05-30
2001-04-03
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S341000, C438S309000
Reexamination Certificate
active
06211029
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device and, more particularly, to a structure of a bipolar transistor and a process of fabrication thereof.
DESCRIPTION OF THE RELATED ART
A bipolar transistor is an important circuit component of a semiconductor integrated circuit device used for a communication network in the giga-helz band. The switching speed of the bipolar transistor is mainly dominated by the thickness of the base region where the carrier passes through. The thinner the base region is, the faster the switching action is. The resistance of the emitter, base and collector regions and the parasitic capacitances coupled to the emitter/base and collector regions affect the switching speed of the bipolar transistor. These factors strongly relate to the miniaturization and the accuracy of patterning technologies used in the fabrication process of the bipolar transistor. However, a self-aligning technology between the emitter region and the base contact region makes the improvement in switching speed free from the accuracy of patterning technologies. The self-aligning technology is disclosed by Tak H. Ning et al. in “Self-Aligned Bipolar Transistors for High-Performance and Low-Power Delay VLSI”, IEEE Transactions on Electron Devices”, vol. ED-28, No. 9, September 1981, pages 1010 to 1013.
FIGS. 1A
to
1
G illustrate a typical example of the process of fabricating the self-aligned bipolar transistor of the n-p-n type. The prior art process starts with preparation of a p-type silicon substrate
1
. A photo-resist ion-implantation mask (not shown) is prepared on the major surface of the p-type silicon substrate
1
by using lithographic techniques, and an area is uncovered with the photo-resist ion-implantation mask. Arsenic is ion implanted into the area, and the photo-resist ion-implantation mask is stripped off. The ion-implanted arsenic is activated in nitrogen ambience at 1000 degrees to 1200 degrees in centigrade for 2 to 4 hours, and forms a heavily doped n-type buried layer
1
b.
A photo-resist ion-implantation mask (not shown) is patterned on the major surface of the p-type silicon layer
1
a
by using the lithographic techniques, and another area around the heavily doped n-type buried region
1
b
is uncovered with the photo-resist ion-implantation mask. Boron is ion implanted into the exposed area, and the photo-resist ion-implantation mask is stripped off. The ion-implanted boron is activated in the nitrogen ambience at 900 degrees to 1100 degrees in centigrade for 30 minutes to an hour, and forms a heavily doped p-type buried region
1
c
as shown in FIG.
1
A. The heavily doped p-type buried region
1
c
electrically isolates the self-aligned bipolar transistor from another circuit component.
N-type silicon is epitaxially grown to 2 microns thick on the major surface of the p-type silicon substrate la, and the p-type silicon substrate
1
a
is overlain by an n-type epitaxial silicon layer
2
a.
A p-type channel stopper region
2
b
is formed in the n-type epitaxial silicon layer
2
a,
and is merged with the heavily doped p-type buried layer
1
c
as shown in FIG.
1
B.
A thick field oxide layer
3
is selectively grown to 600 nanometers thick by using the LOCOS (local oxidation of silicon) technology. The growth of the thick filed oxide layer
3
is carried out at 1000 degrees in centigrade, and consumes long time. While the heat is growing the thick field oxide layer
3
, the boron and the arsenic are diffused from the heavily-doped p-type buried layer/p-type channel stopper region
1
c/
2
b
and the heavily doped n-type buried layer
1
b,
respectively, and the n-type buried layer
1
b
expands as shown in FIG.
1
C. As a result, the expansion of the n-type buried layer
1
b
decreases the thickness of the n-type epitaxial layer
2
a
inside of the thick field oxide layer
3
.
Subsequently, phosphorous is thermally diffused into a narrow area of the n-type epitaxial layer
2
a,
and reaches the heavily doped n-type buried layer
1
b.
The phosphorous forms an n-type collector contact region
4
a
merged into the heavily doped n-type buried layer
1
b.
Silicon oxide is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and forms a silicon oxide layer. A photo-resist etching mask is patterned on the silicon oxide layer through the lithography, and the silicon oxide layer is selectively etched away. The silicon oxide layer is patterned into a silicon oxide mask
5
a.
The n-type collector contact region
4
a
is covered with the silicon oxide mask
5
a;
however, the n-type epitaxial silicon layer
2
a
is exposed to an opening of the silicon oxide mask
5
a
as shown in FIG.
1
D.
Subsequently, polysilicon is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and p-type dopant impurity is introduced into the polysilicon layer. In this instance, boron is introduced into the polysilicon through an in-situ doping technique, or boron is ion implanted into the amorphous silicon layer. The boron-doped polysilicon layer is used for a base electrode as described hereinlater.
In order to isolate the base electrode from an emitter electrode, silicon nitride is deposited over the boron-doped polysilicon layer, and the boron-doped polysilicon layer is overlain by a silicon nitride layer. A photo-resist etching mask (not shown) is patterned on the silicon nitride layer, and the silicon nitride layer and the boron-doped polysilicon layer are selectively etched away so as to form a base electrode
4
b
covered with an inter-level insulating layer
5
b
as shown in FIG.
1
E.
A photo-resist etching mask (not shown) is patterned on the inter-level insulating layer
5
b,
and has an opening over a central area of the n-type epitaxial silicon layer
2
a.
Using the photo-resist etching mask, the inter-level insulating layer
5
b
and the base electrode
4
b
are selectively etched away so as to form an opening
5
c
over the central area of the n-type epitaxial layer
2
a.
The resultant semiconductor structure is treated with heat, and the boron is diffused from the base electrode
4
b
into the central area of the n-type epitaxial layer
2
a.
The boron forms a graft base region
4
c
beneath the base electrode
4
b.
Boron or boron difluoride (BF
2
) is ion implanted into the central area of the n-type epitaxial silicon layer
2
a,
and forms an intrinsic base region
4
d
as shown in FIG.
1
F.
Silicon oxide is deposited over the entire surface of the resultant semiconductor structure, and forms a silicon oxide layer topographically extending over the resultant semiconductor structure. The silicon oxide layer is anisotropically etched away without a photo-resist etching mask, and side wall spacers
5
d/
5
e
are left on the inner and outer side surfaces of the base electrode
4
b.
The side wall spacer
5
d
on the inner side surface covers a peripheral area of the intrinsic base region
4
d,
and an central area of the intrinsic base region
4
d
is still exposed.
Heavily arsenic-doped polysilicon is grown on the entire surface of the resultant semiconductor structure, and a heavily arsenic-doped polysilicon layer is held in contact with the central area of the intrinsic base region
4
d.
A photo-resist etching mask (not shown) is patterned on the heavily arsenic-doped polysilicon layer, and the heavily arsenic-doped polysilicon layer is patterned into an emitter electrode
4
e.
The arsenic is thermally diffused from the emitter electrode
4
e
into the central area of the intrinsic base region
4
d
by using a lamp annealing, and forms an emitter region
4
f.
Finally, a collector contact hole is formed in the silicon oxide layer
5
a,
and a collector electrode
4
g
is held in contact with the corrector contact region
4
a
through the collector contact hole as shown in FIG.
1
G.
Thus, the side wall spacer
5
d
causes the emitter region
4
f
to be exactly nested into the intrinsic base region
4
c,
and the emitter
Hayes Soloway Hennessey Grossman & Hage PC
NEC Corporation
Nguyen Tuan H.
LandOfFree
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