Process of embedded circuit structure

Details Process of embedded circuit structure Process of embedded circuit structure

2011-04-26

2011-04-26

Vinh, Lan (Department: 1713)

Etching a substrate: processes

Forming or treating electrical conductor article

Forming or treating of groove or through hole

C216S013000, C216S018000, C438S624000

Reexamination Certificate

active

07931818

ABSTRACT:
A process of an embedded circuit structure is provided. A complex metal layer, a prepreg, a supporting board, another prepreg and another complex metal layer are laminated together, wherein each of the complex metal layers has an inner metal layer and an outer metal layer stacked on the inner metal layer, the roughness of the outer surfaces of the inner metal layers is less than the roughness of the second outer surfaces of the outer metal layers, and the outer surfaces of the outer metal layers after laminating are exposed outwards. Each of two patterned photoresist layers is respectively formed on the outer surfaces of the outer metal layers. A metal material is created on portions of the outer surfaces of the outer metal layers not covered by the patterned photoresist layers to form two patterned circuit layers. The patterned photoresist layers are then removed to form a laminating structure.

REFERENCES:
patent: 6376052 (2002-04-01), Asai et al.
patent: 2003/0148136 (2003-08-01), Yamamoto et al.
patent: 518616 (2003-01-01), None
patent: I251455 (2006-03-01), None
Chinese Examination Report of Taiwan Application No. 096116845, dated May 12, 2010.

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