Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-05-15
2001-06-19
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S337000
Reexamination Certificate
active
06249154
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to switches, and, more particularly, to insulated-gate field-effect transistors (MOS transistors) of analog/digital (A/D) converters.
BACKGROUND OF THE INVENTION
An analog MOS switch, i.e. a MOS switch intended to transmit analog signals, generally functions by successively turning the MOS transistor on and off by biasing it sufficiently such that its drain-source resistance in the on state (commonly termed R
on
by those skilled in the art) is small in relation to the load capacitance (switched capacitance) connected on its drain, and to the frequency of the analog signal to be transmitted. In order for a MOS transistor to be on, it is necessary as a minimum for the gate-source voltage difference to exceed the threshold Vt of the transistor. Consequently, the analog signal to be transmitted cannot exceed the system supply voltage minus this threshold voltage. Moreover, because the analog input voltage modulates the gate-source voltage of the transistor, the resistance R
on
varies with the level, i.e. the amplitude, of the signal.
Although this variation is only slightly troublesome at low frequencies, it very quickly becomes disturbing and generates distortions at higher frequencies, for example at frequencies of the order of 100 MHZ, especially for high resolution, for example 10 bits in an analog/digital (A/D) converter application, with this elevated frequency. Stated otherwise, the distortion, caused by the variation in resistance R
on
, is manifested as nonlinear restoration of the signal by the switch, in terms of amplitude and phase. Additionally, the larger the amplitude of the input signal, the larger this distortion since the resistance R
on
is inversely proportional to the level of the input signal.
An approach which has already been envisaged includes controlling the switch digitally, i.e. with a logic signal exhibiting a high level and a low level, and by using a particularly elevated high level, for example of the order of twice the supply voltage. This makes it possible to minimize the variations in the level of the input signal, but such a solution is not applicable to the technologies currently envisaged in microelectronics, such as 0.25 micron or 0.18 micron, or even more miniaturized technologies.
Dimensioning approaches may also be envisaged to decrease the product R
on
×C
1
, where C
1
denotes the capacitive value of the load capacitance. However, in most cases, C is imposed by other design constraints, such as noise and consumption, thereby leading to the need to decrease R
on
. However, decreasing this resistance amounts to increasing the size of the transistor forming the switch, and hence to increasing in particular the stray capacitance of the device.
SUMMARY OF THE INVENTION
An object of the invention is to minimize, or even to almost completely eliminate, the distortions of a high-frequency analog signal transmitted through a switch, without increasing the size of the transistor, and in a manner which is entirely compatible with 0.25 micron or 0.18 micron, or even more miniaturized fabrication technology.
The invention therefore provides a process for controlling a switch of a switched-capacitance device, this switch comprising at least one insulated-gate field-effect transistor, for example an N-channel MOS transistor. According to this process, an analog input signal is delivered on the source of the transistor and the transistor is controlled on its gate synchronized with a clock signal so as to successfully turn it on and off.
According to a general characteristic of the invention, on the conclusion of each half-period of the clock signal during which the transistor is off, a precharging capacitor is precharged at the start of the next half-period (termed the conduction half-period) and for a predetermined precharge duration, with a predetermined precharge voltage, then for the remaining duration of the conduction half-period. The precharged capacitor is connected between the source and the gate of the transistor forming the switch so as to turn it on under the action of a gate-source voltage which is almost independent of the level of the input signal. Then, at the end of the half-period, the gate of the transistor and the precharging capacitor are grounded.
Stated otherwise, the MOS transistor of the switch is not controlled digitally, i.e. with a control logic signal having a high state (for example the supply voltage Vdd) and a low state (for example ground), but by using a floating gate-source control voltage which is almost independent of the voltage of the input signal. This floating voltage is obtained by connecting between the gate and the source of the MOS transistor, a capacitor previously precharged with a predetermined precharge voltage.
The person skilled in the art will be able to tailor the precharge duration of the precharging capacitor, and consequently the remaining duration of the conduction half-period as a function of the sought-after effectiveness, given the application envisaged. Indeed, the switched-capacitance device should be steady over a sufficient duration (upon the half-period during which the switch is on) such that the device may be regarded as static in relation to the product R
on
C
1
, where C
1
denotes the capacitive value of the load capacitance (switched capacitance) connected at the output of the switch. By way of indication, the higher the transmission frequency and the larger the sought-after resolution, the longer the remaining half-duration of the conduction half-period will have to be.
In this respect it has been observed that a remaining duration of the conduction half-period at least equal to 1.5 times the time constant R
on
C
1
of the resistive capacitive circuit formed by the drain-source resistance of the transistor in its on state and by the switched capacitance, constituted a minimum below which the effectiveness sought by the invention greatly decreased. Furthermore, it has been deemed preferable for this remaining duration of the conduction half-period to be at least equal to three or four times the time constant. This makes it possible in particular to obtain satisfactory results with an input signal frequency of the order of a few hundred MHz and a resolution of the order of from 10 to 12 bits, and with a clock signal having a frequency of 50 MHz, a frequency corresponding to the sampling frequency of the analog/digital converter.
Moreover, on the conclusion of the precharge duration, when the precharging capacitor is connected floating between the source and the gate of the transistor of the switch, the gate-source voltage is equal to the precharge voltage in the case where the system is devoid of global stray capacitance.
This being so, in practice, this global stray capacitance exists and is more particularly formed by the gate-source capacitance of the transistor and by the stray capacitance existing between ground and the terminal common to the precharging capacitor and to the gate of the transistor of the switch. This global stray capacitance has the consequence, during redistribution of the charges on conclusion of the precharge duration, of leading to a gate-source voltage of the transistor which is below the precharge voltage.
The person skilled in the art will be able to tailor the value of the precharge voltage in such a way that the gate-source voltage during toggling on the conclusion of the precharge duration remains greater than the threshold voltage of the transistor forming the switch (so that it is on) given the value of the stray capacitance and of the gate-source capacitance of the transistor. In practice, it will advantageously be possible to choose a precharge voltage at least equal to twice the threshold voltage of the transistor.
The process according to the invention applies equally well in a variant in which the switched-capacitance device comprises only one input for receiving the input signal, as in a variant using a differential mode, i.e. in which the input signal has a direct component and a complemente
Jouffre Pierre-Olivier
Paillardet Frederic
Telliez Isabelle
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Nu Ton My-Trang
STMicroelectronics S.A.
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