Process of compensating for layer thickness by determining...

Details Process of compensating for layer thickness by determining... Process of compensating for layer thickness by determining...

2003-01-15

2004-08-03

Abraham, Fetsum (Department: 2826)

Semiconductor device manufacturing: process

With measuring or testing

C438S216000, C438S275000, C257SE21530

Reexamination Certificate

active

06770494

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to characterizing and accommodating chip planarity or surface flatness profile across a die or chip. More particularly, the present invention relates to accommodating the flatness profile in a product or device design.
2. Background Information
Experimental data and available literature identify and verify that chemical mechanical polishing (CMP) across a die results in a non-uniform thickness profile. The non-uniformity depends on the polish recipe and the device layout. More specifically, regarding device layout, the device density, aspect ration, area, and pitch, inter alia, contribute to this non-uniform thickness.
The thickness of a film layer, say an oxide, on a die that is subject to CMP can be measured where the variations in the film thickness can be correlated and reproduced as a function of device layout. Here the density (referred to as “loading” in the art) of the devices and the area of the raised structures in the immediate area will affect the oxide thickness. It is well documented in the literature associated with this art that where the density of structures is lower the removal rate of oxide is greater resulting in relatively thinner oxide layer. This effect is illustrated with the Preston equation where the removal rate (RR) is equal to the Preston coefficient (K) multiplied by the pressure (P) and the relative velocity (V), or RR=KPV. Pressure is higher in lower density areas of a chip and accordingly the RR is higher.
One known approach, suggested by the density observation above, is to increase the number of structures across a chip to make the loading uniform. In this case the RR will be more uniform, but at the expense of using valuable chip space with non-functioning or dummy structures. Another limitation of this technique is that the loading near the edges and corners of the chip remains lower than the center of the chip due to the form factor, and so the thickness at the perimeter of the chip will still be thinner than at the center. Moreover, devices at the perimeter may still be unusable.
Another approach is to design specific polish recipes for particular devices and layouts, but this is cumbersome and inefficient in practical production processes.
The use of dummy structures, mentioned above, to compensate for non-uniformity is disclosed in a number of U.S. patents. For example, U.S. Pat. Nos. 6,265,315; 6,259,115; 6,054,362; and 5,965,941. All share the limitation of consuming chip space with non-functioning device.
A technical paper entitled,
Impact of CMP ILD Thickness Variation on Interconnect Capacitance and Circuit Performance
, by Nakagawa et al., Feb. 13-14, 1997 at the CMP-MIC conference, describes a modeling process and technique to predict CMP variations. Such techniques may be used in conjunction with the present invention as described below, and this paper is incorporated by reference herein.
Another prior art technical article is entitled,
Using a Statistical Metrology to Identify Systemic and Random Sources of Die and Wafer Level ILD Thickness Variations in CMP Processes
, by Chang, E et al., 1995 at the International electron Devices Meeting. This article suggests using a statistical metrology framework to characterize CMP variations, to improve process control and interconnect simulation for designing robust circuits. This framework can be used for predicting circuit performance variations caused by layout factors and CMP variations across the chip.
The above references suggest approaches to minimize but not eliminate the thickness variations across a chip. None provide or suggest a solution to the reduced device yields due to the limitations of thinner layers near the edges of chips.
SUMMARY OF THE INVENTION
The present invention addresses the limitations in the prior art by providing for the characterizing of CMP thickness variations across a chip and accepting these variations as design factors used to optimize a device's performance across the entire surface of a chip. The present invention provides an approach that eliminates or substantially reduces the loss of devices near the edges of a die or chip and thus improves the yields of the devices on a chip.
The problem of the prior art is discussed with respect to a chip, but the present invention provides advantages for systems that may use entire wafers.
In a preferred embodiment, the angle of mirrors fabricated on to a chip surface when latched into position is a function of the thickness of usually an oxide layer. However, by characterizing the thickness variations on the chip the distances from the upright support to the mirror hinge may be selected to form an array of mirrors across a chip all with an acceptably equal angle.
In yet other preferred embodiments of electronic components where thickness are important, for example capacitors, other parameters may be selected, for example plate area of capacitors, so that equal value capacitors are produced regardless of location on a chip.


REFERENCES:
patent: 5965941 (1999-10-01), Weling et al.
patent: 6054362 (2000-04-01), Chuang
patent: 6159073 (2000-12-01), Wiswesser et al.
patent: 6259115 (2001-07-01), You et al.
patent: 6265315 (2001-07-01), Lee et al.
patent: 6301009 (2001-10-01), Tinker
patent: 6323982 (2001-11-01), Hornbeck
Chang, E. et al., Using a Statistical Metrology Framework to Identify Systematic and Random Sources of Die- and Wafer-level ILD Thickness Variation in CMP Processes, IEEE, 1995.
Stine, B. et al., Rapid Characterization and Modeling of Pattern-Dependent Variation in Chemical-Mechanical Polishing, IEEE Transactions on Semiconductor Manufacturing, 1998, pp. 129-140, vol. II, No. 1.
Liu, G. et al., Chip-Level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films, SemiWorld Journal, vol. 5.

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