Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
1999-04-21
2001-11-13
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331S025000, C327S007000, C327S156000, C348S537000, C375S376000
Reexamination Certificate
active
06317005
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process of clock recovery during the sampling of digital-type signals, more especially a process making it possible to recover the clock during the sampling of video signals emanating from a computer device.
BACKGROUND OF THE INVENTION
The sampling of video signals emanating from an analog source is well known. It uses the Shannon-Nyquist theorem. According to this theorem, if the passband of a signal is limited to a frequency range such as [0,Fmax], it is necessary and sufficient to sample this signal at a minimum frequency 2×Fmax in order to be capable of reconstructing it from these samples. This constraint is manifested by the introduction of low-pass filters whose purpose is to limit the spectrum of the signals before sampling. In this case, the phase of the clock signal is of no importance in the sampling procedure. Indeed, the same signal sampled by two clocks of the same frequency but which are out of phase contains the same information to within a constant lag.
The same does not hold when having to sample video signals emanating from a computer device, namely, signals of digital origin. Indeed, the spectrum of these signals is very wide and they are intended to be viewed under the highest possible resolution. Accordingly, the passband must not be limited since there would be a loss of fineness. If signals of this type have to be injected into a device which comprises a sampling stage, the following problems arise:
If the inbound signal is filtered so as to limit its passband and satisfy the Nyquist criteria, the response of the filter to digital-type signals exhibiting steep transitions will engender overoscillations which are very prejudicial to the sharpness of the characters.
If the inbound signal is hardly filtered so as to avoid overoscillation, the attenuation afforded to the frequency components will be insufficient to avoid a likewise prejudicial spectral aliasing.
If the inbound signal is sampled without prior filtering, it is imperative to adopt not only the exact frequency which served to generate the signal but also a sampling phase corresponding to the middle of each porch.
The problem is all the more complex since there is no predefined fixed standard in this area. Indeed, in the displaying of video signals emanating from a graphics card, only the number of active pixels per line of the source and the number of active lines per image of the source are defined. Accordingly, the total number of pixels per line, the total number of lines as well as the image frequency and the pixel frequency are not standardized. Similarly, the phase of the first active pixel with respect to the edge of the synchronizing clock is not defined, neither linewise nor imagewise.
BRIEF DESCRIPTION OF THE INVENTION
Accordingly, the purpose of the present invention is to propose a process making it possible automatically to recover the frequency parameter and phase parameter of the sampling clock in the case of the sampling of digital-type signals, more especially of video signals emanating from a computer-type device.
The subject of the present invention is a process of clock recovery during the sampling of computer-type signals, the sampling clock being generated from a phase locked loop or PLL which multiples a given frequency by an integer number or “division rank”, characterized in that it comprises the following steps:
gauging of the position of the edges of the computer-type signals with respect to the sampling clock with the aid of an analog ramp triggered by the rising edges of the computer-type signals in such a way as to obtain a first value dependent on the said position,
carrying out of a sampling clock phase correction,
by comparing the first position-dependent value with a reference value in such a way as to obtain a second signed value,
by accumulating the second signed values during the given frequency,
by transforming the accumulated values into an analog value dependent on the sampling phase-shift and by applying the value thus obtained to the PLL so as to phase-shift the sampling clock, and
carrying out of a frequency correction,
by measuring the alteration in the phase error between two consecutive analog ramps,
by determining and accumulating the sign of this alteration,
then, when the accumulated value exceeds a positive or negative threshold value, by sending an increment of +1 or −1 depending on the threshold value in relation to the division rank of the PLL.
According to another characteristic of the present invention, the gauging of the position of the edges of the digital-type signals is preceded by an operation of reshaping the said transitions. This reshaping is carried out by filtering the digital-type signals with the aid of a high-pass filter and by comparing the amplitude of the filtered signals with a voltage threshold. Preferably, the comparison is carried out by a voltage comparator with hysteresis and the gauging of the position of the edges is carried out by applying the analog ramp to an analog/digital converter whose clock signal is the sampling clock.
When carrying out the phase correction and in order to avoid needless operations, before the comparison, the values corresponding to an absence of utilizable transition and the values corresponding to an overly old transition, namely one prior to the current sampling period are set to the reference value.
Likewise, before carrying out the frequency correction, the values used are applied to a circuit making it possible to eliminate the zero values corresponding either to a zero phase error, or to an absence of rising transition, or to an absence of falling transition.
According to a further characteristic of the present invention, an initial division rank is calculated as a function of the standard to which the digital-type signals to be sampled belong. This prior calculation makes it possible to accelerate the convergence during correction of the sampling frequency.
Although the convergence procedure is faster on a video template consisting of a white/black alternation at the pixel frequency, this particular condition is not absolutely necessary for the proper operation of the device. Any video template exhibiting per image a number of video transitions regularly distributed along the horizontal axis of the image which is at least equal to twice the error in the division rank makes it possible to guarantee convergence, even if these transitions are distributed over several lines. Moreover, if the above criterion is not complied with (non-compliance with the Nyquist criterion) but the sampling of the phase error function takes place at instants randomly distributed along the whole of the line, convergence may also be obtained.
REFERENCES:
patent: 5297869 (1994-03-01), Benham
patent: 5657089 (1997-08-01), Onogawa
patent: 0807923A1 (1997-11-01), None
patent: 0519739A1 (1992-12-01), None
patent: 0660611A2 (1995-06-01), None
Morel Philippe
Tapie Thierry
Grimm Siegfried H.
Shedd Robert D.
Thomson Licensing S.A.
Tripoli Joseph S.
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