Process monitor for CMOS integrated circuits

Details Process monitor for CMOS integrated circuits Process monitor for CMOS integrated circuits

1994-08-09

1996-01-23

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Compensation for variations in external physical values

327 35, 327 38, 327175, H03K 1714, H03K 908

Patent

active

054867860

ABSTRACT:
A process monitor for a CMOS integrated circuit includes first and second delay units that are connected in a ring to constitute a ring oscillator that generates pulses having different phases at the outputs of the delay units respectively. The delay units affect the frequency of the pulses and also the rising and falling edges of the pulses differently depending on the process factor of PMOS and NMOS transistors in the delay units. The process factor can be computed from the frequency, or the ratio of the phase differences between the rising and falling edges of the pulses at the outputs of the first and second delay units. The oscillatory configuration of the monitor is highly sensitive to variations in process factor, and enables the monitor to be embodied by a relatively small number of elements that can fit in two input/output slots in a standard integrated circuit layout.

REFERENCES:
patent: 4710653 (1987-12-01), Yee
patent: 5019782 (1991-05-01), Schatter
patent: 5068547 (1991-11-01), Gascoyne
patent: 5359301 (1994-10-01), Candage
patent: 5365204 (1994-11-01), Angiulli et al.

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