Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification
Reexamination Certificate
2011-06-21
2011-06-21
Levin, Naum (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Analysis and verification
C716S054000, C430S005000, C430S030000
Reexamination Certificate
active
07966580
ABSTRACT:
A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the mask pattern by using each of the process models to predict a plurality of model patterns; calculating a difference in dimension between the test pattern and each of the model patterns; extracting a model pattern in which the difference in dimension from the test pattern is within a scope of specification from the model patterns; and specifying the process model, which predicts the extracted model pattern, as the mask pattern.
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Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Levin Naum
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