Process-model generation method, computer program product,...

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification

Reexamination Certificate

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C716S054000, C430S005000, C430S030000

Reexamination Certificate

active

07966580

ABSTRACT:
A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the mask pattern by using each of the process models to predict a plurality of model patterns; calculating a difference in dimension between the test pattern and each of the model patterns; extracting a model pattern in which the difference in dimension from the test pattern is within a scope of specification from the model patterns; and specifying the process model, which predicts the extracted model pattern, as the mask pattern.

REFERENCES:
patent: 6902855 (2005-06-01), Peterson et al.
patent: 7065738 (2006-06-01), Kim
patent: 7342646 (2008-03-01), Shi et al.
patent: 2005/0149902 (2005-07-01), Shi et al.
patent: 2005/0210437 (2005-09-01), Shi et al.
patent: 2006/0161452 (2006-07-01), Hess
patent: 2004-157160 (2004-06-01), None
patent: 2004-246223 (2004-09-01), None

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