Process-insensitive controllable CMOS delay line

Details Process-insensitive controllable CMOS delay line Process-insensitive controllable CMOS delay line

1998-01-23

2000-04-25

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327271, 327272, 327284, 327285, H03H 1126

Patent

active

060548843

ABSTRACT:
A delay cell for use in binary delay line which includes a delay circuit having N outputs where N.gtoreq.2, each delay circuit coupled to an input through N-1 serially connected unit cells. For each output there are P unit cells having a unit delay of t.sub.P0 and N-1-P unit cells having a unit delay of t.sub.p1. The N outputs are ordered such that each output other than the first is delayed with respect to an immediately preceding output by t.sub.p1 -t.sub.p0, and P goes in succession from N-1 to 0 in unit steps. Each value of P corresponds to only one of the N outputs.

REFERENCES:
patent: 5295174 (1994-03-01), Shimizu
patent: 5489867 (1996-02-01), Tamanoi

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