Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-01-12
2002-10-29
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
Reexamination Certificate
active
06472914
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of charge pump phase-locked loop circuitry; and, in particular, to process independent ultralow charge pump used in phase locked loop (PLL) for phase error correction.
BACKGROUND OF THE INVENTION
The charge-pump phase-locked loop (CP-PLL) is widely used in modern fully integrated circuits and is implemented in various applications; e.g. modulation, demodulation, detection, clock recovery, synchronization or frequency synthesis. Specifically, CP-PLLs are used in high speed transmitters and receivers operating at 2.5 Gb/sec used for Ethernet and high speed switching, switch network and fiber channels. The demand for a fast data switching and less input/output pins on a chip has created a need for a charge pump that can operate given these conditions.
The CP-PLL is a phase servo-system whose basic high level components include a phase and frequency detector, a charge-pump, a loop filter and a voltage controlled oscillator (VCO). The phase and frequency detector is purely a digital device having up and down voltage outputs. The charge pump, connected to the phase and frequency detector, delivers a pump current which is driven by the up and down voltage outputs of the phase and frequency detector. The loop filter, coupled to the charge pump, is generally a low-pass filter for converting the pump current into an analog voltage which is used to control the digital output of the voltage controlled oscillator. In essence, the charge pump provides the tuning voltage for the voltage controlled oscillator to generate a very stable, low noise local oscillator signal. A good overview of charge-pump PLL circuits is given in “High-Level Modeling applied to the Second-Order Charge-Pump PLL Circuit,” by Hedayat et. al., TI Technical Journal, p.99-107, March-April 1997. The disclosure of the foregoing reference is incorporated herein.
A phase-locked loop design based upon a self-biased technique achieves process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation and most importantly, low input tracking jitter. The key idea behind self-biasing is that it allows circuits to choose the operating bias levels in which they function best. A good overview of the theory of low-jitter process-independent phase-locked loop designs is given in “Low-Jitter Process-Independent DLL and PLL based on Self-Biased Techniques,” by John G. Maneatis, IEEE Journal of Solid-State Circuits, Vol. No. 11, November, 1996. The disclosure of the foregoing reference is incorporated herein.
The self-biased design phase-locked loop and delay-locked loop both require a charge pump current that will vary several decades over the operating frequency range. The self-bias design includes a bias generator coupled between the charge pump and the VCO. Self-biasing makes it possible to design a charge pump that has zero static phase offset when both the up and down voltage outputs of the phase and frequency detector are asserted for equal duration on every cycle with in-phase inputs.
The known charge pump disclosed in the aforementioned reference is composed of two NMOS source coupled pairs each with a separate current source and connected by a current mirror made from symmetric load elements. Charge will be transferred from or to the loop filter connected to the output of the charge pump when the up and down voltage outputs, respectively, are switched high.
With both the up and down outputs asserted, the left source-coupled pair will behave like a half-buffer replica such as the one included in the known bias generator. The left source-coupled pair will produce the control voltage V
CTRL
at the current mirror node. The PMOS device in the right source coupled pair will have the control voltage V
CTRL
coupled at its gate and drain which is connected to the loop filter. This device will then source the exact same buffer bias current that is sunk by the remainder of the source coupled pair. With no net charge transferred to the loop filter, the charge pump will have zero static phase offset.
Given the relationship of the up and down charge pump output currents integrated over time, the area under both voltage output curves is equivalent. The slope with respect to amplitude, however, is not the same for both voltage output curves. Accordingly, a substantial amount of phase noise exists, since the up voltage output increases at a faster rate than the down voltage output.
In addition, the range of operation that exists for this known charge pump is between 0.1 mA to 1 mA. Thus, this charge pump roughly tunes the signal. There exists a need for a charge pump that tracks performance variation and more finely tunes the phase-locked loop. In addition, there is a need for a noise-free charge pump that tracks and recovers data from a GHz data stream.
SUMMARY OF THE INVENTION
A charge pump, having increased precision over known charge pumps, for a self-biasing phase-locked loop and a self-biasing delay-locked loop includes a p-type charge pump and a n-type charge pump. The charge pump has inputs for an up and a down voltage output from a phase and frequency detector and for at least two bias voltage outputs from a bias generator. The p-type charge pump is coupled to the up output of the phase and frequency detector and a first bias voltage output from the bias generator circuit. The n-type charge pump is coupled to the p-type charge pump and has inputs coupled to the down output of the phase and frequency detector and a second bias voltage output from the bias generator circuit. A first capacitor is coupled across the p-type charge pump. This charge pump operates between 1 &mgr;A to 10 &mgr;A. It is a more balanced design than known charge pump designs. Although PMOS is slow, the present implementation of both the p-type and the n-type charge pumps pull up and pull down at the same time. This charge pump can be used with very narrow bandwidths. As another advantage, due to the up voltage output of the phase and frequency detector increasing at a rate approximate to current down voltage output, a relatively small amount of phase noise exists. With reference to phase error correction, this charge pump implementation more finely tunes the output signal of the phase locked loop design.
REFERENCES:
patent: 5532636 (1996-07-01), Mar et al.
patent: 6111469 (2000-08-01), Adachi
patent: 6160432 (2000-12-01), Rhee et al.
patent: 6222421 (2001-04-01), Kiyose
patent: 6316977 (2001-11-01), Sargeant
Christian D. Hedayat et al., High-Level Modeling Applied to the Second-Order Charge-Pump PLL Circuit,Engineering Technology, Mar.-Apr. 1997, p. 99-107.
John G. Maneatis, Low-Jitter Process Independent DLL and PLL Based on Self-Biased Techniques, IEEE Journal of Solid-State Circuits, vol. NO. 11, Nov. 1996 p.1723-1732.
Gu Richard X. W.
Tran James M.
Brady W. James
Mosby April M.
Zweizig Jeffrey
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