Process for wafer level treatment to reduce stiction and...

Details Process for wafer level treatment to reduce stiction and... Process for wafer level treatment to reduce stiction and...

2007-05-22

2007-05-22

Baumeister, B. William (Department: 2891)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S052000, C438S056000, C257SE21261

Reexamination Certificate

active

10457500

ABSTRACT:
This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.

REFERENCES:
patent: 3713886 (1973-01-01), Fulton et al.
patent: 4781942 (1988-11-01), Leyden et al.
patent: 5061049 (1991-10-01), Hornbeck
patent: 5130265 (1992-07-01), Battilotti et al.
patent: 5331454 (1994-07-01), Hornbeck
patent: 5429708 (1995-07-01), Linford et al.
patent: 5578863 (1996-11-01), De Poorter
patent: 5694740 (1997-12-01), Martin et al.
patent: 5766367 (1998-06-01), Smith et al.
patent: 5801309 (1998-09-01), Carr et al.
patent: 5822170 (1998-10-01), Cabuz et al.
patent: 5904952 (1999-05-01), Lopata et al.
patent: 5923995 (1999-07-01), Kao et al.
patent: 5936758 (1999-08-01), Fisher et al.
patent: 5950101 (1999-09-01), Yano et al.
patent: 6063714 (2000-05-01), Smith et al.
patent: 6265026 (2001-07-01), Wang
patent: 6287430 (2001-09-01), Matsumoto et al.
patent: 6335224 (2002-01-01), Peterson et al.
patent: 6358771 (2002-03-01), Martin et al.
patent: 6379988 (2002-04-01), Peterson et al.
patent: 6969635 (2005-11-01), Patel et al.
Favia et al., J. of Polymer Science Part A: Polymer Chem., vol. 32, Issue 1, pp. 121-130, (1994).
Parylene Coatings, by Beach et al., pp. 789-801 in Electronics Materials Handbook; vol. 1, Packaging, Minges et al., Eds, ASM International (1989).
Oct. 04, 2000—Slide presentation by J. Martin to American Vacuum Society Meeting, Boston, MA (abstract included).
Oct. 9, 2000—Slide presentation by J. Martin to Worcester Polytechnic Institute, Worcester, MA (abstract included).
Mar. 14, 2000—Slide presentation by J. Martin to National Institute of Standards and Technology, Gaithersburg, MD.
Handbook of Electronic Package Design, Edited by Michael Pecht, CALCE Center for Electronic Packaging, University of Maryland at College Park, Maryland, Marcel Dekker, Inc., copyright 1991, pp. 21-23 and pp. 767-772.

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