Process for transmitting signals between two chips with high-spe

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307205, 307303, 307304, 307DIG1, H03K 1760, H03K 1908

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active

040029280

ABSTRACT:
Two semiconductor chips having complementary MOS circuits are interconnected by means of an output stage provided on the first chip and an input stage provided on the second chip. The connection is a high-speed connection despite the relatively high internal impedance of the MOS transistors. The output stage incorporates MOS transistors for transforming the signal level to a relatively low level, and the input stage incorporates MOS transistors interconnected as a pulsed trigger or amplifier for restoring the low signal to a relatively high level for connection to other MOS circuits.

REFERENCES:
patent: 3588527 (1971-06-01), Cricchi
patent: 3590273 (1971-06-01), Jarvis
patent: 3673438 (1972-06-01), Lund
patent: 3675043 (1972-07-01), Bell
patent: 3676700 (1972-07-01), Buchanan
patent: 3731114 (1973-05-01), Gehweiler
patent: 3739200 (1973-06-01), D'Agostino
patent: 3801831 (1974-04-01), Dame
patent: 3835457 (1974-09-01), Yu
IBM Tech. Disc. Bulletin, vol. 16, No. 5, 10/1973, "Low-Power Gated Receiver", by Chin et al.

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