Process for the simultaneous production of self-aligned bipolar

Details Process for the simultaneous production of self-aligned bipolar Process for the simultaneous production of self-aligned bipolar

1986-11-17

1988-04-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437 33, 437233, 437191, 437195, 148DIG9, 148DIG124, 357 43, 357 59, 357 34, 156653, H01L 2700, H01L 2128, H01L 21302

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047374721

ABSTRACT:
A process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate wherein n-doped zones are produced in the p-doped substrate and insulated npn-bipolar transistors are formed into the n-doped zones. The n-zones form the collectors of the transistors and are modified according to conventional technology by additional process steps such that bipolar transistors are formed which are self-aligning both between the emitter and the base and also between the base and collector with extremely low-ohmic base terminals consisting of polysilicon and a silicide. Storage capacitances can also additionally be integrated into the structure. The use of the base terminals thus produced permits very small lateral emitter-collector distances. The combination of dynamic CMOS memory cells with fast bipolar transistors is made possible by the integration of the storage capacitances. The process is used for the production of VLSI circuits of high switching speeds.

REFERENCES:
patent: 4290186 (1981-09-01), Klein et al.
Motorola "The Epic Process" Motorola Monitor vol. 2, #2 Jun. 64.

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