Process for the reception of a binary digital signal

Details Process for the reception of a binary digital signal Process for the reception of a binary digital signal

1989-10-04

1991-03-26

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

328109, H04L 700

Patent

active

050035614

ABSTRACT:
A process for receiving a binary digital signal by a method for the reception of a binary digital signal, which may also have phase shifts, with a supplied clock that may have any desired phase position with respect to the digital signal and may deviate somewhat in frequency from the bit sequence frequency of the digital signal. From the clock (T1) there is formed over a delay chain (7-13, 52-55) a series of clocks (T2-T12), which have approximately equal phase intervals. Short pulses (I11-I110) are derived from the clocks (T1-T12). T12). Upon the arrival of each edge of a digital signal (D1) that has been selected as the effective edge, there is derived a read pulse (I21) which may also be delayed (I2x), with which the presence of pulses (I11-I110) may be determined through AND gates (20-25, 60-63). Through SR flip-flops (26-31, 64-67) and AND gates (32-37, 68-71), clocks (F1-F10) selected with the pulses (I11-I110) that are present are switched through and OR-linked (38) for use as an input clock (Te). The total delay of this process step is, if necessary, dimensioned in such a way by delaying the read pulse (I2) that the effective edge of the input clock (Te) occurs always one half clock period after the effective edge of the digital signal (D1). An application of the invention is in synchronous switching matrices and in block switching.

REFERENCES:
patent: 3593160 (1971-07-01), Moore
patent: 3819853 (1974-06-01), Stein
patent: 3961138 (1976-06-01), Fellinger
patent: 4288874 (1981-09-01), Yamada
patent: 4385395 (1983-05-01), Tanaka et al.
patent: 4780891 (1988-10-01), Guerin et al.
PCT International Publication WO 88/05236, dated Jul. 14, 1988.

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