Process for the production of bipolar transistors and complement

Details Process for the production of bipolar transistors and complement Process for the production of bipolar transistors and complement

1986-11-17

1988-06-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 44, 437 59, 437193, 357 59, 357 43, 148DIG9, H01L 21265

Patent

active

047525894

ABSTRACT:
A process for the simultaneous production of bipolar transistors and CMOS transistors on a substrate using very large circuit integration (VLSI) semiconductor technology, modified by additional process steps in such a way that a decoupling of the two types of transistors is obtained with respect to the process. This is achieved by the use of a protective oxide above the active zones of the CMOS transistors during the production of the bipolar-specific base zones and by employing a gate electrode material in two layers, the second layer being used for the emitter and collector zone, resulting in a decoupling of phosphorus doping used for forming MOS gates, and arsenic doping used for polysilicon emitters. The use of the same resist mask for the gate structuring and the production of the emitter contact, and also for the production of the source/drain terminal zones, serves to keep the implanted phosphorus out of the emitter zone. The process is used to produce VLSI circuits containing high speed CMOS and bipolar transistors.

REFERENCES:
patent: 4637125 (1987-01-01), Iwasaki et al.
Alvarez et al. "2 Micron Merged Bipolar--CMOS Technology" 1984 IEDM Technical Digest pp. 761-764.
Wieder, "Self-Aligned Bipolar Technology-New Chances for Very-High Speed Digital Integrated Circuits" Siemens Forsch-u. Entwickl-Ber Bd 13 (1984).
Murrmann, "Modern Bipolar Technology for High-Performance ICs" Siemens Forsch-u. Entwickl Ber Bd 5 (1976).
Miyamoto et al., A 1.0um N-Well CMOS/Bipolar Technology for VLSI Circuits, IEE (1983).
Jacobs et al., "N- and P-Well Process Compatibility in a 1.mu.m CMOS Technology" IEDM (1984).

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