Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Utility Patent
1998-05-21
2001-01-02
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S771000, C438S788000
Utility Patent
active
06168961
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a process for preparing epitaxial wafers for analysis and, more particularly, to a process for the preparation of a surface of a p-type or a n-type epitaxial semiconductor wafer for capacitance-voltage measurements.
Semiconductor wafers suitable for the fabrication of integrated circuits are produced by slicing thin wafers from a single crystal silicon ingot. After slicing, the wafers undergo a lapping process to give them a somewhat uniform thickness. The wafers are then etched to remove damage and produce a smooth surface. The final step in a conventional wafer shaping process is a polishing step to produce a highly reflective and damage-free surface on at least one face of the wafer. It is upon this polished face that electrical device fabrication takes place.
The performance of electrical devices fabricated from silicon wafers can be enhanced through epitaxial deposition. Epitaxial deposition is the process of growing a thin crystalline layer on a crystalline substrate. For example, a lightly doped silicon epitaxial layer can be grown over a heavily doped silicon substrate wafer. Such a structure allows for high device operating speeds at moderate currents. Other advantages of epitaxy include precise control of dopant concentration profiles and freedom from impurities.
The epitaxial layer is deposited by placing a substrate wafer in an epitaxial reactor and then introducing into that reactor by means of a carrier gas, such as hydrogen, one of a number of silicon-based compounds, including SiCl
4
, SiHCl
3
, or SiH
2
Cl
2
. Once the desired operating conditions are achieved, silicon deposition occurs as the result of a reaction between the silicon-based compound and the hydrogen carrier gas which produces hydrochloric acid and pure silicon. The silicon which is produced is then deposited on the substrate wafer surface. Deposition may continue until an epitaxial layer of the desired thickness has been grown.
After epitaxial layer deposition is complete, typically certain characteristics of the wafer are evaluated at or near the intended device region of the wafer. Epitaxial layer characteristics such as dopant concentration profile, resistivity, slope, flat zone, etc. are indications of the quality of the layer. These epitaxial layer characteristics are most commonly measured by capacitance-voltage (“CV”) techniques which involve first preparing a Schottky diode.
Preparation of a Schottky diode involves forming an electrical circuit by means of two contacts with the surface of the material to be tested. Typically, a Schottky diode comprises contacting the silicon wafer with a column of liquid mercury on the epitaxial layer side and with a metal plate, such as a steel plate, on the non-epitaxial side. These contacts may be formed using conventional instrumentation and methods, including the “front side down” method (see, e.g., MSI instrument, commercially available from MSI) and the “back side down” method (see, e.g., SSM instrument, commercially available from Solid State Measurement).
Capacitance-voltage measurements are performed by continuously changing the applied potential to the surface of the wafer. Experience has shown that the surface state of the wafer to be tested may strongly influence the properties of the Schottky diode used for the CV measurements. This influence is primarily due to the fact that majority carriers present in the wafer may flow through, or migrate across, the junction which is formed at the mercury-silicon interface of thus diode. As a result, the reliability of the measurement may be compromised. To prevent this migration from occurring, the junction must be maintained in a rectifying state. Typically, this rectifying state is achieved by chemically treating the wafer surface by means common in the art (see, e.g., ASTM Recommendation F1392).
The method of chemical treatment employed depends upon the type of wafer to be treated. For example, for a n-type wafer, chemical treatment typically involves forming, or growing, a thin oxide layer on the wafer surface. Oxide layer growth is typically achieved by immersing the wafer for several minutes in a solution containing an oxidizing agent, such as nitric acid, hot hydrogen peroxide or ozonated water. The wafer is then rinsed in deionized water for about 10 minutes and spun dry in an atmosphere of nitrogen.
For a p-type wafer, chemical treatment typically involves either treating the wafer for about 30 seconds in a concentrated HF solution, or treating the wafer for about 5 minutes in a dilute HF solution (such as, for example, a solution of 1 part HF to 10 parts water). The wafer is then rinsed for about 10 minutes with deionized water and spun dry in an atmosphere of nitrogen.
These current methods of preparing the surface of a n-type or p-type epitaxial wafer are problematic for a number of reasons. First, the use of highly acidic solutions poses safety hazards in a production environment and the vapors which result from heating such solutions are harmful to surrounding equipment. Second, throughput is decreased because these methods are time consuming, primarily due to the fact that these are “wet bench” methods requiring wafer drying before further processing can be performed. Third, expensive equipment is required to handle solutions of this kind and to obtain adequate surface preparation. Lastly, in the case of p-type wafer preparation, large quantities of hydrofluoric acid are consumed which significantly adds to the expense of the process.
In view of the foregoing, a need continues to exist for an efficient and cost-effective process by which to prepare the surface of a n-type or a p-type wafer, such that accurate and consistent CV measurements may be obtained. The ability to accurately and efficiently monitor the performance of epitaxial reactors in a continuous manner is critical to the production of epitaxial wafers because, if the wafers being produced have unacceptable dopant concentration profiles, the epitaxial reactor can be adjusted to prevent the further production of such unacceptable wafers.
SUMMARY OF THE INVENTION
Among the objects of the present invention, therefore, are the provision of an improved process for evaluating the characteristics of a silicon wafer having a n-type or a p-type epitaxial layer on the surface thereof; the provision of such a process wherein the wafer surface which is to be evaluated is not wetted; and, the provision of a process for preparing a n-type or a p-type epitaxial wafer for capacitance-voltage measurements which allows for increased safety, efficiency, and cost effectiveness.
Briefly, therefore, the present invention is directed to a process for evaluating a silicon wafer having a n-type or a p-type epitaxial layer on the surface thereof. In a first embodiment, an oxide layer is formed on the surface of a n-type epitaxial wafer by exposing the wafer to ultraviolet light while in the presence of oxygen. The wafer is then subjected to a capacitance-voltage measurement to evaluate the characteristics of the epitaxial layer.
The present invention is further directed to a process for evaluating surface characteristics of a silicon wafer having a n-type epitaxial layer on the surface thereof. Ozone and atomic oxygen are formed by irradiating an oxygen-containing atmosphere with ultraviolet light, the ultraviolet light having wavelengths of about 185 nm and about 254 nm. A n-type epitaxial wafer is exposed to the ozone and atomic oxygen to form a silicon oxide layer on a surface of the wafer. The wafer is then subjected to a capacitance-voltage measurement to evaluate the characteristics of the epitaxial layer.
The present invention is further directed to a process for evaluating surface characteristics of a silicon wafer having a n-type epitaxial layer on the surface thereof. The process comprises forming a silicon oxide layer on top of the epitaxial layer by exposing the wafer to ultraviolet light while in the presence of oxygen, the ultraviolet light having wavelengths of ab
Booth Richard
MEMC Electronic Materials , Inc.
Senniger Powers Leavitt & Roedel
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