Process for the manufacture of power-MOS semiconductor devices

Details Process for the manufacture of power-MOS semiconductor devices Process for the manufacture of power-MOS semiconductor devices

1990-12-24

1992-08-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 41, 148DIG126, H01L 21265

Patent

active

051418835

ABSTRACT:
A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.

REFERENCES:
patent: 4489481 (1984-12-01), Jones
patent: 4677735 (1987-07-01), Malhi
patent: 4716126 (1987-12-01), Cogan
patent: 4735680 (1988-04-01), Yen
patent: 4757032 (1988-07-01), Contiero
patent: 4772569 (1988-09-01), Ishii et al.
patent: 4774198 (1988-09-01), Contiero et al.
patent: 4798810 (1989-01-01), Blanchard et al.
patent: 4842675 (1989-06-01), Chapman et al.
patent: 4902636 (1990-02-01), Akiyama et al.
patent: 4949136 (1990-08-01), Juin
patent: 4985740 (1991-01-01), Shenai et al.
"The Application of Ion Beam Mixing, Doped Silicide, and Rapid Thermal Processing to Self-Aligned Silicide Technology", J. Electrochem. Soc., vol. 137, No. 2, Feb. 1990, pp. 728-740.
"Optimized Silicon Low-Voltage Power MOSFET's for High Frequency Power Conversion" Krishna Shenai, et al. IEEE 1989, pp. 180-189.
"High-Performance Vertical-Power DMOSFET's With Selectively Silicided Gate and Source Regions", Krishna Shenai et al., IEEE Electron Device Letters, Apr. 10, 1989, No. 4, New York, pp. 153-155.
"Experimental Technology and Characterization of Self-Aligned . . . ", G. A. Sai-Halasz et al., International Electronic Devices Meeting, Dec. 6-9, 1987, Washington, D.C., pp. 397-400.

Affiliated with

Also associated with

Rating

Process for the manufacture of power-MOS semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for the manufacture of power-MOS semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for the manufacture of power-MOS semiconductor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-384623