Process for the manufacture of III-V semiconductor devices

Details Process for the manufacture of III-V semiconductor devices Process for the manufacture of III-V semiconductor devices

1989-01-12

1991-01-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 33, 437 41, 437126, 437133, 437 90, 437 91, 437107, 148DIG11, 148DIG65, 148DIG72, H01L 2190

Patent

active

049818082

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention concerns improvements in or relating to processes for the manufacture of III-V semiconductor devices--e.g. bipolar and field-effect transistor devices. Especially, reference will be made to gallium arsenide (GaAs)/gallium aluminium arsenide (GaAlAs) heterostructure bipolar transistors. Other III-V homostructure and heterostructure materials, however, will be mentioned as also other device types.


BACKGROUND ART

The theoretical performance advantages of gallium arsenide (GaAs)/gallium aluminium arsenide (GaAlAs) III-V bipolar transistors over their silicon counterparts are well known. At present, however, higher bipolar circuit speeds have been obtained for silicon devices. There is one reason for this discrepancy: highly advanced silicon technology makes possible the fabrication of devices of extremely small size hitherto unattainable with current GaAs processes. In particular, the "Super Self-Aligned" process (Sakai T., et al., "Prospects of SSI technology for high speed LSI", IEDM 1985, Tech. Dig., p18.) represents the state of the art for silicon.
There are considerable obstacles to the realisation of such a process in GaAs; silicon has intrinsic advantages such as a native oxide, the possibility of polycrystalline silicon overgrowth for extended contacts and impurity diffusion, and a common contact metallurgy for p-type and n-type regions. Published schemes for self-alignment of GaAs/GaAlAs bipolar devices (e.g. Asbeck P.M., "Heterojunction Bipolar Transistors", IEDM 1985, Short course: Digital III-V Device and Circuit Technology", course notes p114., and, Izawa T., et al., "AlGaAs/GaAs Heterojunction Bipolar Transistors", IEDM 1985, Tech. Dig., p328.) have suffered from difficulties involved in contacting the base layer due to the need to remove any parasitic GaAs/GaAs homojunction regions between emitter and base. Achieving a low contact resistance to the emitter is also problematic. Scaling to the dimensions typified by the self-aligned silicon device (above) presents great problems in these schemes.


DISCLOSURE OF THE INVENTION

The present invention is intended as a remedy to the problems outlined above and provides a process suited for producing highly self-aligned devices with small feature geometry, i.e. devices, comparable thus in geometry and size to state-of-the-art silicon devices.
In accordance with this invention, thus, there is provided a process for the manufacture of a III-V semiconductor device, this process including the steps of: insulating material; the etch, and, the surface of the underlying material exposed by the etch, a further and conformal layer of insulating material; underlying material whilst leaving insulating material covering the top and side aforesaid; growing a layer of lattice matched material upon the surface of the underlying material thus exposed, the same to provide a first extended contact region, the upper surface of this grown layer lying below the top of the structure aforesaid; insulating material; and, structure aforesaid.
In the manner aforesaid insulation is provided between the first and second extended contacts by means of overgrown insulating material. Also, insulation is afforded between the structure material aforesaid and the first extended contact by the sidewall insulating material remaining following the anisotropic etch.
In the method aforesaid and in particular for bipolar transistor manufacture, the growth of the lattice matched material for extended contact formation may be preceded by masked implantation, this step being essential to afford electrical continuity to a buried base layer, part of the structure.
The composition of the III-V semiconductor structure, insulating materials and extended contact materials may be varied as appropriate, depending on device type and application. Alternatives will be considered in the description that follows.


BRIEF INTRODUCTION OF THE DRAWINGS

In the drawings accompanying this specification:
FIGS. 1 to 7 are cross-sections showing heterostructure geometry at

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patent: 4619036 (1986-10-01), Havemann et al.
patent: 4731340 (1988-03-01), Chang et al.

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