Process for the manufacture of a high density cell array of gain

Details Process for the manufacture of a high density cell array of gain Process for the manufacture of a high density cell array of gain

1992-12-16

1994-05-03

Thomas, Tom

Fishing, trapping, and vermin destroying

437 40, 437 47, 437 60, 437200, 437904, 437915, H01L 2170

Patent

active

053087836

ABSTRACT:
A multistep process is disclosed that provides an economical process for making a gain memory cell array using self-aligned techniques; that provides an integrated diode in the gate stack of the storage transistor; that provides a buried V.sub.DD line to connect the drains of the storage transistors to the power supply; and that provides a buried strap to connect the integrated diode to the source region of the storage transistor.

REFERENCES:
patent: 4416404 (1984-10-01), Wang et al.
patent: 4432073 (1984-02-01), Masuoka
patent: 4543595 (1985-09-01), Vora
patent: 4631705 (1986-12-01), Honda
patent: 4654825 (1987-03-01), Rinerson
patent: 4914740 (1990-04-01), Kenney
patent: 5021849 (1991-06-01), Pfiester et al.

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