Process for the fabrication of silicon transistors with high DC

Details Process for the fabrication of silicon transistors with high DC Process for the fabrication of silicon transistors with high DC

1975-01-31

1976-03-09

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148 15, 357 34, 357 63, 156 17, H01L 21223

Patent

active

039430146

ABSTRACT:
A monocrystalline silicon wafer is prepared which has formed therein the usual emitter, base and collector regions. A groove is then formed to a predetermined depth in the top surface of the silicon wafer so as to extend along the P-N junction between the base and emitter regions. A silicon oxide layer is formed over the wafer, as by heating the same in an oxidative atmosphere, and the wafer is succeedingly heated in a hydrogenous atmosphere. The silicon oxide layer may be selectively photoetched away where the electrodes are to be formed for the emitter, base and collector of the transistor.

REFERENCES:
patent: 3426253 (1969-02-01), Roque et al.
patent: 3772577 (1973-11-01), Planey
patent: 3858234 (1974-12-01), Olson

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