Process for the fabrication of integrated structures including n

Fishing – trapping – and vermin destroying

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437 26, 437 37, 437 46, 437 52, 437 61, 357 235, H01L 2126

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active

047191848

ABSTRACT:
After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.

REFERENCES:
patent: 4373249 (1983-02-01), Kosa
patent: 4495693 (1985-01-01), Iwahashi

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