Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Field plate electrode
Reexamination Certificate
2001-03-09
2003-10-28
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Field plate electrode
C438S738000, C438S942000
Reexamination Certificate
active
06638833
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a process for the fabrication of integrated devices with reduction of damage from plasma.
BACKGROUND OF THE INVENTION
For the fabrication of the integrated devices which are on the market at present, the monocrystalline silicon wafers are subjected to a plurality of physical and chemical treatments which make it possible to define the topographies of the integrated electronic circuits.
In particular, for definition of electronic components in submicrometric technologies, extensive use is made of a process technique which is known as plasma etching, which makes it possible to etch thin films, both of conductive materials and dielectric materials.
A known example of application of the plasma etching technique is illustrated in
FIGS. 1-3
, in which a portion of a wafer
1
comprises a substrate
2
of semiconductor material and a layer of sensitive material
3
on top of the substrate
2
; the layer of sensitive material
3
can for example be a layer of dielectric material, a layer of polycrystalline silicon, or a layer of metallization, which must be defined by means of plasma etching.
As illustrated in
FIG. 2
, on top of the layer of sensitive material
3
, a mask
4
is produced in order to protect the portions which are not to be removed, of the layer of sensitive material
3
itself.
In particular, the mask
4
is produced from a known material such as photoresist or resist material, which consists of photosensitive organic polymers.
As illustrated in
FIG. 3
, after the plasma etching has been carried out, a defined layer
3
of sensitive material is obtained.
During the plasma etching, an equal quantity of positive ions and electrons is directed towards the wafer
1
, but in individual areas of the wafer there are two mechanisms which lead to separation of the electric charges on the wafer
1
, i. e.:
lack of uniformity of the plasma itself, as a result of which more negative than positive charges reach certain areas on the wafer, whereas in other areas the contrary applies; and
the electron shading effect.
The electron shading effect is the effect according to which a part of the negative charges is implanted in the mask, instead of reaching the layer to be etched, whereas most of the positive charges reach it successfully. This gives rise to separation of electric charges, and thus to generation of an electric field, which can cause damage to the layer of sensitive material
3
.
It is considered that the electron shading effect is caused by the lower weight, and therefore by the greater thermal agitation of the electrons themselves. Thus, whereas the positive ions have a prevalently vertical speed vector, and reach directly the surface of the layer to be etched, the electrons also have a significant horizontal component, which means that some of the electrons collide with the upper portion of the mask
4
, and do not reach the layer of sensitive material
3
to be etched.
A detailed description of the electron shading effect is described for example in the articles: “Reduction of the charging damage from electron shading,” by K. Hashimoto, Y. Hikosaka, A. Hasegawa and M. Nakamura, in 1996 1st International Symposium on Plasma Process-induced Damage, May 13-14, Santa Clara, Calif. 1996 American Vacuum Society; “On the link between electron shadowing and charging damage,” by Gyeong S. Hwang and Konstantinos P. Giapis, in J. Vac. Sci. Technol. B 15(5), Sep./Oct. 1997; “Charge damage caused by electron shading effect,” by K. Hashimoto, in Jpn. J. Appl. Phys. Vol. 33 (1994), Part 1, No. 10, Oct. 1994, p 6013.
The electron shading effect is disadvantageous owing to the fact that the positive charges on the layer of sensitive material
3
to be etched recall electrons from the substrate
2
beneath, thus giving rise to a passage of current in the structures of the devices.
The electric currents which pass through the thin oxides of electronic devices can damage the latter, modifying their properties and giving rise to problems of functioning of the devices themselves, or reducing their reliability over a period of time.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a process which can reduce to a minimum, or even eliminate the damage from plasma caused by the electron shading effect.
According to the present invention, a layer to be etched is formed on the surface of a semiconductor substrate. A non-conductive mask is formed on the surface of the layer on which the plasma etch procedure is to be performed. At some time, a conductive outer layer is provided for the mask. In one embodiment, the conductive outer layer is provided before the etching begins. In an alternative embodiment, the etching is performed for a period of time, interrupted, the conductive outer layer provided, after which the etching is resumed.
The semiconductor substrate is protected from damaged caused by parasitic electrical currents by virtue of the fact that the electrons that fail to reach the layer can propagate through the conductive mask and recombine with the positive charges that strike the layer. As a result, parasitic currents are reduced or eliminated in the substrate.
REFERENCES:
patent: 5387556 (1995-02-01), Xiaobing et al.
patent: 5795829 (1998-08-01), Shen
patent: 5843848 (1998-12-01), Yanagawa
patent: 5962341 (1999-10-01), Ito
patent: 5976986 (1999-11-01), Naeem et al.
patent: 6090722 (2000-07-01), Armacost et al.
patent: 6197689 (2001-03-01), Tabara
patent: 6420099 (2002-07-01), Gutsche et al.
patent: 6451705 (2002-09-01), Trapp et al.
patent: 0710977 (1996-05-01), None
patent: 0874395 (1998-10-01), None
Hummel Rolf E. Electronic Properties of Materials 3rd ed., Springer Verlag 2001, pp. 166-174.*
Hwang et al., “On the link between electron shadowing and charging damage,”J. Vac. Sci. Technol. B 15(5):1839-1842, Sep./Oct. 1997.
Siu et al., “Effect of plasma density and uniformity, electron temperature, process gas, and chamber on electron shading damage,” Lam Research Corporation, Fremont. CA.
Hashimoto et al., “Reduction of the charging damage from electron shading,”1996 1stInternational Symposium on Plasma Process-Induced DamageMay 13-14, Santa Clara, CA., 1996 American Vacuum Society.
Hashimoto, Koichi, “Charge damage caused by electron shading effect,”Jpn. J. Appl. Phys. vol. 33, Part 1(10):6013-6018, Oct. 1994.
Alba Simone
Vassalli Omar
Carlson David V.
Jorgenson Lisa K.
Le Vu A.
Luhrs Michael K.
SEED IP Law Group PLLC
LandOfFree
Process for the fabrication of integrated devices with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for the fabrication of integrated devices with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for the fabrication of integrated devices with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3162076