Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Patent
1992-12-28
1995-02-14
Williams, Howard L.
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
341144, H03M 176
Patent
active
053899288
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
The present invention concerns a procedure for the conversion of digital codes, and more in particular of signed binary codes, that is codes where the word is made of N bits, one of which constitutes the sign bit.
The invention concerns also a digital-to-analog converter having high resolution and operation frequency higher than one MHz, in particular a two-phase converter where the more significant bits of the code word are converted first, and the less significant ones thereafter.
This converter is preferably of the single supply type and suitable to integration in CMOS technology.
A two-phase or two-step digital-to-analog converter using a mixed technique (resistive-capacitive) is known, where the decoding of the more significant M bits is made through a voltage demultiplexing or a "potentiometric" conversion, while the remaining less significant K bits are decoded with a charge switching technique.
Generally, a fully potentiometric converter employs a resistive network (or resistor string) consisting of 2.sup.N elements (where N is the number of bits) operating as a stepping potentiometer, supplied at the ends by two reference voltages Vref+ and Vref-, whose different voltage levels are selected by a switch decoding matrix, controlled by the bits to be decoded.
Such an architecture enables one to obtain a very high conversion speed, but is practicable only for low resolutions. For the number of bits equal to 8 it presents, in fact, some drawbacks due to the complexity of the voltage divider and of the switching logic needed. With 8 bits it is necessary to employ a resistive string consisting of 256 definite elements, whose implementation in the integrated form turns out to be difficult since it involves the covering of a large area on the chip, and furthermore the accuracy required for the string elements is critical.
A conversion circuit with a full charge switching topology employs a binary weighted capacitor matrix sequentially injecting, in the virtual ground of an operational amplifier, a charge quantity proportional to a reference voltage and to the digital input word.
Even this conversion technique shows some drawbacks when the resolution increases since, for a comparatively high number of bits (8-10), it requires a great number of capacitive values.
This involves, besides a considerable area increase, a slowing down of the slew rate of the amplifier and a decrease of the gain-bandwidth figure, placing an upper limit on the operation frequency in the range of several hundred MHz.
The mixed architecture represents, therefore, a good compromise for the realization of average resolution converters (9-11 bit) having a conversion speed of several MHz.
The advantage as for resolution arises from the fact that the first M bits are intrinsically monotonic, while the capacitor matrix has to a meet a matching and a monotonic accuracy equal to K bits only to perform an M+K bit conversion. However, as the required resolution increases, that is as the number of bits forming the code increases, this technique is subject to the troubles mentioned above for each one of the two conversion types.
The object of the present invention is to further improve the resolution which can be obtained with this mixed architecture (that is, to increase the total number of bits forming the binary code) while limiting the drawbacks mentioned above for the two conversion techniques, when the bit number increases.
This object is achieved with the present invention, which consists of a process for the conversion of a binary digital signed code made of N bits, one of which represents the sign, characterized by the following steps: analog ground level and an upper full scale level, the maximum range of each one of these voltages being equal to 1/4 of the peak-to-peak voltage to be reconstructed; to its maximum amplitude, so to obtain two voltages, the first of which never has negative polarity, while the second one never has positive polarity, one-half of the amplitude of each being equal to one-half amplitude of the fi
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patent: 4618852 (1986-10-01), Kelley et al.
patent: 4661802 (1987-04-01), Yukawa
patent: 4665380 (1987-05-01), Lewyn
patent: 4973979 (1990-11-01), Ikeda
Proceedings of the IEEE 1989, Custom Integrated Circuits Conf., May 15-18, 1989, Castello et al., "Analog Front-End of an ECBM Transceiver for ISDN".
Coppero Luciana
Maloberti Franco
Palmisano Giuseppe
Italtel Societa Italiana Communicazioni, S.P.A.
Williams Howard L.
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