Process for testing integrated circuits with at least one logic

Details Process for testing integrated circuits with at least one logic Process for testing integrated circuits with at least one logic

1994-05-26

1996-04-30

Canney, Vincent P.

Excavating

G01R 3128

Patent

active

055131875

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention relates to a process for testing integrated circuits having at least one logic circuit with a logic network surrounded by boundary-scan cells.
For testing integrated logic circuits and subassemblies fitted with logic circuits, the boundary-scan process is used. The logic circuits which can be tested by this process have at their signal inputs and their signal outputs test stages (boundary-scan cells) which in each case include a change-over switch and at least one memory stage. The input test stages and the output test stages are able to be connected as a shift register chain. Also, all the shift register chains of a plurality of logic circuits arranged on one subassembly can be interconnected in series. The boundary-scan process is described in the Journal "electronic" in a series of continuing articles in Issue 12 (pages 52 to 57) / 13 (pages 102 to 108) / 14 (pages 96 to 103) / 15 (pages 69 to 74) and 17 (pages 62 to 68) 1989. With the aid of the boundary-scan process, the connecting lines from the plug connector of the subassembly to the terminals (inputs and outputs) of the integrated modules and connecting lines between the integrated modules and the connections to the terminals can be checked. Similarly, it is possible furthermore to test the functions of the logic circuits of the integrated modules. For this purpose, test combinations are written in series to the shift registers. The output combination of the logic circuit is transferred into the output test stages, read out and checked. This may also take place with a correspondingly extensive test program in the case of complete switching subassemblies. Until now, only a static test of the built-in logic circuits was carried out, if such a test was performed at all.
Although the use of test multiplexers which are connected into the signal lines also permits a real-time testing of the logic circuits, they require a high outlay due to additional terminal points and complicated wiring.
Test methods for logic circuits are described in the printed document IBM Journal of Research and Development, 34 (1990) March/May, No. 2/3, Armonk, N.Y., U.S., Pages 299 to 312. The equivalent circuit diagram of a large-scale circuit, represented in FIG. 1, comprises two logic networks which are separated from each other by shift-register trigger circuits. Run-time tests are carried out for the integrated large-scale circuit and its various parts. Thus, FIG. 2 shows the use of the shift-register trigger circuits forming double trigger-circuit cells in a boundary-scan arrangement for the dynamic testing of logic networks. In FIG. 10 (Page 307, top) the testing of a logic network between the shift-register trigger circuits is represented. For this purpose, use is made in each case of cells comprising two memory stages L1, L2, in the first memory stage of which initially test information is written serially in the boundary-scan process. The test information written to the first trigger circuits L1 is transferred by a second clock into the second trigger circuits L2, which are connected directly upstream of the inputs of the logic network. With a following clock of a further clock signal, the output information of the logic network is transferred into further double trigger-circuit cells. Nothing is said about the switching of the double trigger-circuit cells in the case of operation.
The run-time test between data inputs PIs and data outputs POs according to FIG. 6 is carried out in a known way without use of boundary-scan cells by direct applying of the test information and comparison of the output information with the expected result in a test device. If a plurality of these logic circuits are connected in a chain, a dynamic testing of the individual circuits becomes virtually impossible however, since neither can the data inputs be supplied with the necessary test information nor is the output information directly accessible to the logic circuits.


SUMMARY OF THE INVENTION

The object of the invention is to specify a proces

REFERENCES:
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5220281 (1993-06-01), Matsuki
"A Logic Chip Delay-Test Method Based On System Timing", Motika et al, IBM Journal of Research & Development, vol. 34, No. 2/3, Mar./May 1990, United States, pp. 299-312.
Standardmassiges Testen Komplexer Systeme: Teil 1: Elemente des hierarchischen Tests, Pete Fleming et al, Elektronik (1989), Germany, pp. 52-57.
Standardmassiges Testen Komplexer Systeme: Teil 2: Vorteile des hierarchischen Tests, Pete Fleming et al, Elektronik (1989), Germany, pp. 102-108.
Standardmassiges Testen Komplexer Systeme: Teil 3: Bustreiber und Latches mit JTAG-Testports, Horst Jungert et al, Elektronik (1989), Germany, pp. 96-103.
Standardmassiges Testen Komplexer Systeme: Teil 4: Entwurf mit JTAG-Testport, Lee Whetsel et al, Elektronik (1989), Germany, pp. 69-74.
Standardmassiges Testen Komplexer Systeme: Teil 5: ASSET-Software Fur JTAG-Testsysteme, Bernhard Geisberger, Elektronik (1989), Germany, pp. 62-68.

Affiliated with

Also associated with

Rating

Process for testing integrated circuits with at least one logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for testing integrated circuits with at least one logic , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for testing integrated circuits with at least one logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-634761