Metal fusion bonding – Process – With measuring – testing – indicating – inspecting – or...
Reexamination Certificate
2000-04-18
2002-04-09
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
With measuring, testing, indicating, inspecting, or...
C029S836000, C029S840000
Reexamination Certificate
active
06367678
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention pertains to the technological sector that deals with the preparation and production of “multilayer” printed circuits, i.e., circuits that consist of a number of layers or flat boards stacked one on top of the other, to each of which is affixed a portion of the circuit, which circuit is implemented and made functional by assembling and outfitting the above-mentioned boards.
More specifically, above-mentioned “multilayer” printed circuits are made up of various layers stacked one on top of the other, each pair of which is a laminate that is made up of two sheets of copper that contain a spacer layer of dielectric material inserted between them.
Each layer is an actual circuit on which two faces are produced by photographic and chemical processes, the tracks and the pads.
Multilayer circuits are produced by soldering together a stack of layers one on top of the other with pre-preg sheets between them, a material composed of woven fiberglass and epoxy resin.
Production is done by successively stacking the layers in which mechanical references, holes, or pits have been made.
In order to estimate the total residual error of this method, allowance is made for the inherent error of mechanical pairing, as well as the error of the machine that produces it.
The standard recording error is never less than 100 microns.
On the outer layers are applied a resin sheet and then a sheet of copper, and then the stack is brought to a temperature and pressure such that it melts the resin that is inserted between the different layers, thus creating a single compact circuit that contains said layers.
The pads that are present in the various layers are traversed by holes which, once coated with metal, will ensure electrical continuity between the various layers. In order to ensure electrical continuity, one hole must pass through all of the pads that are present on the various layers.
The relentless drive toward higher circuit interconnection densities, which is due to the incessant development of new electronic components, is leading to a search for solutions that make it possible to make more tracks and more holes in a smaller area.
The decisive factors for increasing interconnection densities are the width of the tracks and the size of the holes.
Less apparent but still important are the sizes and positions of the pads.
The advantage of producing small-diameter holes is completely negated if, because the locations of the pads are not known, it is necessary to make them larger in order to be sure of connecting them all to a hole.
Since pads located on different layers have to be interconnected, it is necessary that the stacking of said layers be done in an extremely precise fashion.
In current embodiments, the circuit that is to be produced is brought to the drilling machine by means of two cylindrical pins that are inserted into two opposing holes made on the circuit. The positions of the pins must therefore be such as to guarantee proper drilling and thus proper interconnection of all the layers.
For this purpose an x-ray measurement is made of the positions of the references that are present on each layer that comprises the circuit.
The references may be pads or targets and may be stacked on top of one another or offset.
The hole for the pin is made at a location such as to guarantee the interconnection of the various pads (typically the barycenter of the machine, which is visible on x-rays in the case of opposing references, is selected).
The error depends on various factors, especially the measurement error that relates to the x-ray-table-TeleCamera system, and the drilling error. The standard error of this machine varies from 75 to 200 microns and thus has to be considered relevant.
SUMMARY OF THE INVENTION
The inventor of this invention has conceived of a new process that makes it possible to reduce significantly (by a factor of approximately 10) the order of magnitude of the multilayer circuit drilling and stacking error, thereby avoiding the need to take the above-mentioned x-ray measurements.
This process exploits the electromagnetic induction that is exerted between two flat circuits arranged in parallel, in one of which an alternating induction current of appropriate frequency is caused to flow; the voltage that is induced in the other circuit has an amplitude that relates to the amplitude of induction and to the characteristics that vary according to the relative positions between the two facing circuits.
By making the two above-mentioned facing circuits such that one is on a reference board (or slider) and the other is on each of the layers that are to be positioned, if there is an appropriate system for comparing and amplifying the characteristics of the induced voltages and the currents that flow, it is possible to record the position of each layer that is to be positioned in such a way that its circuit is superimposed on that of the slider in a preset relative position.
It is then possible from time to time to remove each perfectly oriented layer and transfer it by means of known precision moving devices that preserve its orientation with respect to the exact position that said layer must assume so that it can, along with the others, form the multilayer circuit that is to be produced.
The object of this invention is, as a matter of fact, a process for positioning relatively correctly a set of parallel stacked layers that constitute a multilayer circuit as described in the preamble to attached claim
1
, characterized by the characterizing part of said claim.
A description will now be given of a preferred embodiment of the process of the invention, but this example should be neither considered limiting nor binding with respect to other implementations that can be produced by one skilled in the art based on the teachings contained in said claim
1
.
REFERENCES:
patent: 4443278 (1984-04-01), Zingher
patent: 4578279 (1986-03-01), Zingher
patent: 4931354 (1990-06-01), Wakino et al.
patent: 5008619 (1991-04-01), Keogh et al.
patent: 5796587 (1998-08-01), Lauffer et al.
patent: 5850109 (1998-12-01), Mock et al.
patent: 6229124 (2000-02-01), Trucco
patent: 196 18 254 (1997-10-01), None
Ballado Investments Inc.
Dunn Tom
Edmondson L.
Young & Thompson
LandOfFree
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