Process for self aligning a source region with a field oxide reg

Details Process for self aligning a source region with a field oxide reg Process for self aligning a source region with a field oxide reg

1990-11-29

1992-06-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 69, 437984, H01L 2176

Patent

active

051206714

ABSTRACT:
A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process. This method and apparatus is particularly appropriate for use with EPROM, Flash EPROM, EEPROM, or other types of memory cells and in periphery devices.

REFERENCES:
patent: 4620361 (1986-11-01), Matsukawa et al.
patent: 4814286 (1989-03-01), Tam
patent: 4861730 (1989-08-01), Hsia et al.
Ghandhi, S. K., "VLSI Fabrication Principles", pp. 499-509, pp. 534-541, 1983.

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