Process for self-aligned source for high density memory

Details Process for self-aligned source for high density memory Process for self-aligned source for high density memory

1995-07-11

1996-09-03

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 41, 437 43, 437 48, 437 52, H01L 21265

Patent

active

055523315

ABSTRACT:
An improved method for protecting the gate edge and adjacent source region of a semiconductor device is disclosed. In this method, spacers are formed along the gates of one type of transistor to protect the gate edge and adjacent source area during a self-aligned source etch. Spacers of a different width, which may be optimized for different voltage requirements, are formed along the gates of a second type of transistor of the same intergated circuit. This method is particularly applicable in the formation of EPROM, Flash EPROM, EEPROM, or other memory cells in conjunction with periphery devices needing to sustain relatively higher voltages. By decouplng the memory cell requirement from the periphery device requirement, tighter gate spacing and smaller cell size can be achieved.

REFERENCES:
patent: 5147813 (1992-09-01), Woo
patent: 5200350 (1993-04-01), Gill et al.
patent: 5439835 (1995-08-01), Gonzales

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