Process for self-align contact

Details Process for self-align contact Process for self-align contact

1994-05-31

1995-07-04

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257751, 257754, 257757, 257763, 257764, 257773, 437190, 437192, 437194, 437203, 437228, 437235, H01L 2348, H01L 2144

Patent

active

054303281

ABSTRACT:
A method and structure for manufacturing a self-aligned contact, for connecting conductive lines to active regions in a silicon substrate, is described. There is a first insulating layer over the silicon substrate, with openings over the active regions. A barrier metal layer is formed over the active regions, along surfaces of the openings, and over a portion of the horizontal surfaces of the first insulating layer in the region adjacent to the openings. There is a refractory metal layer over the barrier metal layer. Conductive lines are self-aligned over the barrier metal layer and over the refractory metal layer. Sidewall spacers are formed adjacent to the conductive lines and over those regions of the refractory metal layer not covered by the conductive lines.

REFERENCES:
patent: 4713356 (1987-12-01), Hiruta
patent: 4804560 (1989-02-01), Shioya et al.
patent: 4898841 (1990-02-01), Ho
patent: 4906593 (1990-03-01), Shioya et al.
patent: 5212400 (1993-05-01), Joshi
patent: 5300813 (1994-04-01), Joshi et al.

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