Process for selective area growth of III-V semiconductors

Details Process for selective area growth of III-V semiconductors Process for selective area growth of III-V semiconductors

1998-11-23

2001-01-30

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

C438S039000, C438S040000

Reexamination Certificate

active

06180429

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods for the selective deposition of III-V semiconductors for use in processing electronic and optoelectronic devices.
BACKGROUND OF THE INVENTION
Processing of III-V semiconductors includes vital steps for depositing III-V materials on selected areas of the device substrate. Additive processes are well known and usually take the form of one of two general approaches. Chemically active gaseous species can be made to deposit preferentially on a semiconductor surface, and not deposit on a masking layer. Somewhat more versatile, because they are relatively material independent, are lift-off techniques, where material is blanket deposited on the intended region of the substrate as well as on the mask, but the mask is raised sufficiently that the deposited layer forms with a disconnect at the step between the portion on the substrate and the portion on the mask. When the mask is removed the material deposited on the mask easily lifts off.
III-V heterostructure devices typically have many semiconductor layers. For example, a multiquantum well (MQW) laser has a minimum of six layers, i.e. active multiquantum well layers, two waveguide layers, two cladding layers, and a contact layer. For process simplicity, reduced contamination and lower cost, the multiple layers are typically deposited in a single sequential operation. This produces a relatively large multilayer stack. The active device area is defined by etching around a portion of the multilayer stack to produce a mesa stripe. Passivating the resulting mesa, where sensitive junction regions are exposed at the surface, usually requires deposition of a passivating material. Mesas in typical heterostructure transistor manufacture can be passivated using insulating materials, such as SiO
2
, which permits relatively straightforward deposition approaches. However, in heterostructure lasers, the device performance is determined by the optical as well as electrical properties of the sidewall interface and regrown layers, and thus requires a compatible optical material to fill the region around the multilayer mesa. Accordingly, it is customary to grow a III-V epitaxial semiconductor blocking layer on the substrate and the sidewalls of the mesa.
Selective area growth processes of both categories mentioned above are candidates for the purpose just described. Preferential deposition techniques using metal-organic chemical vapor deposition (MOCVD) or chemical beam epitaxy (CBE) have been used. Under the proper growth conditions, precursors of the blocking layer material can be made to react with the semiconductor substrate and the semiconductor sidewall to grow epitaxial material on the mesa sidewall, while not reacting with the mask material (typically silicon dioxide or silicon nitride).
A drawback to these chemical processes is that they involve hazardous gases. They have other limitations as well. In the case of CBE, the typical precursor materials contain organic constituents and result in unwanted carbon doping of the semiconductor. In MOCVD, the growth temperatures are high, resulting in mass transport of the layers, and undesired diffusion in the multilayer stack. Moreover, the relatively poor directionality of the depositing material requires a large mask overhang to obtain effective lift-off, leading to dimensional control problems.
We propose using all solid-source molecular beam epitaxy (MBE) which does not use toxic gases, and does not have the same control and diffusion problems as the chemical processes just described. However, known MBE approaches that are adapted for this application have problems also. Due to the near unity sticking of group III constituents, material deposits rapidly on the mask as well as on the substrate and mesa sidewalls. Even with a relatively thick mask, material deposited on the mask grows over the mask edge and connects to the material growing from the sidewall. When this material, which is not of epitaxial quality, mixes with epitaxial material growing from the substrate, the crystal quality of the overall layer deteriorates. Moreover, when these regions grow together, lift-off is no longer effective.
It would appear that a solution to these problems would be to use a large overhang on the lift-off mask. Techniques for producing overhangs are available, and are reasonably straightforward to implement. However, a large overhang also has a large shadow. The overhang interferes with pre-cleaning the sidewall prior to deposition. Also, a large overhang excessively masks the sidewalls during deposition.
SUMMARY OF THE INVENTION
We propose a modified masking layer that addresses the concerns just outlined. The modified mask uses a III-V semiconductor spacer layer under the primary mask layer. The modified mask is used in an etch step, which is non-selective among the semiconductor layers, to define the mesa structure, and in a selective etch step for lift-off patterning after epitaxial regrowth of the blocking layer. The modified mask enables use of MBE for the regrowth step and thus allows the entire epitaxial growth process to be done using MBE.


REFERENCES:
patent: 5251225 (1993-10-01), Eglash et al.
patent: 5506170 (1996-04-01), Yodoshi et al.
patent: 5789275 (1998-08-01), Lee et al.
patent: 5863811 (1999-01-01), Kawai et al.

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