Process for running programs with selectable instruction...

Details Process for running programs with selectable instruction... Process for running programs with selectable instruction...

2003-07-01

2009-11-10

Bullock, Jr., Lewis A (Department: 2193)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S149000, C712S215000

Reexamination Certificate

active

07617494

ABSTRACT:
The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions, which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order. There is defined a sequence of execution of the instructions in successive operating cycles of the processor system, assigning each sub-bundle to an operating cycle, thus preventing simultaneous assignment to the same operating cycle of two sub-bundles belonging to the first set of two successive bundles. The instructions of the sequence may be executed by the various processors of the system in conditions of binary compatibility.

REFERENCES:
patent: 5031096 (1991-07-01), Jen et al.
patent: 5129077 (1992-07-01), Hillis
patent: 5634135 (1997-05-01), Hollander
patent: 5787302 (1998-07-01), Hampapuram et al.
patent: 5951674 (1999-09-01), Moreno
patent: 6044450 (2000-03-01), Tsushima et al.
patent: 6272481 (2001-08-01), Lawrence et al.
patent: 6298370 (2001-10-01), Tang et al.
patent: 6367067 (2002-04-01), Odani et al.
patent: 6615339 (2003-09-01), Ito et al.
patent: 6651082 (2003-11-01), Kawase et al.
patent: 6792560 (2004-09-01), Francis et al.
patent: 6799266 (2004-09-01), Stotzer et al.
patent: 6892293 (2005-05-01), Sachs et al.
patent: 6950926 (2005-09-01), Menezes
patent: 6988183 (2006-01-01), Wong
patent: 7062634 (2006-06-01), Southwell et al.
patent: 2003/0200421 (2003-10-01), Crook et al.
patent: 2004/0039900 (2004-02-01), Heishi et al.
patent: 2004/0054882 (2004-03-01), Borneo et al.
patent: 0 768 602 (1997-04-01), None
patent: 0 924 603 (1999-06-01), None
patent: 1 102 166 (2001-05-01), None
patent: 1 152 329 (2001-11-01), None
patent: 1 324 191 (2003-07-01), None
patent: 2332075 (1999-09-01), None
patent: WO 00/33186 (2000-06-01), None
patent: WO 01/53933 (2001-07-01), None
Biglari-Abhari, M., et al. “Improving Binary Compatibility in VLIW Machines through Compiler Assisted Dynamic Rescheduling,” Proceedings of the Euromicro Conference, Sep. 5-7, 2000, pp. 386-393, Euromicro 26, vol. 1, Los Alamitos, CA.

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