Process for removing dopant ions from a substrate

Details Process for removing dopant ions from a substrate Process for removing dopant ions from a substrate

2001-10-05

2004-07-20

Markoff, Alexander (Department: 1746)

Cleaning and liquid contact with solids

Processes

For metallic, siliceous, or calcareous basework, including...

C134S011000, C134S030000

Reexamination Certificate

active

06764551

ABSTRACT:

BACKGROUND OF THE INVENTION
The present disclosure relates to device fabrication and in particular, to a process for removing dopant ions from a semiconductor substrate.
In device fabrication, dopant or impurity ions are introduced into the semiconductor material to alter its electrical conductivity. One technique of introducing dopant ions into the semiconductor material is with an ion implanter. An ion implanter typically uses a high current accelerator tube equipped with steering and focusing magnets to bombard the surface of the semiconductor material with dopant ions to impart the desired electrical properties. These dopant ions are implanted into the top layer of the semiconductor material and just below the surface, changing the conductivity of a precise region. To create a p-type region, an acceptor ion such as boron, gallium or indium is implanted. To create an n-type region, a donor ion such as antimony, arsenic, phosphorous or bismuth is implanted.
As the ions enter the material, they collide with target atoms and come to rest at an average depth below the surface of the substrate. The average depth at which the ions are distributed varies with the implant energy as well as with the target material and the species of ion being implanted. For a given target material and ion species, higher energy generally corresponds to a deeper penetration of the ions into the material. The dose or the total number of ions entering the target is controlled by monitoring the ion current during implantation as well as the time of implantation.
A variation of conventional ion implantation is a plasma ion immersion process, wherein the material itself is placed directly in the plasma source while applying an accelerating bias (on the order of a few kV) to the material. This is an attractive alternative to conventional ion implantation techniques as high dose rates (in the range of 10
15
/cm
2
min) can be achieved at lower energies with less cost intensive ion implantation equipment modification. Typically the target to be implanted is placed directly in the plasma and then biased to a negative potential in order to sufficiently accelerate positive ions into the target for implantation.
Gaseous diffusion of dopants is another method employed to form doped regions. A gas or vapor containing the desired dopants is deposited onto the wafer and then thermally diffused into the substrate surface, such as by chemical vapor deposition.
An alternative to ion implantation and gaseous diffusion processes is the use of a doped dielectric film as a dopant diffusion source. In this alternative approach, a doped dielectric film such as boron silicate glass or arsenic silicate glass, is deposited onto a substrate and used as a source of dopant ions which are diffused into the substrate to form doped regions. For example, doped dielectric films are deposited at temperatures less than 500° C. in a deposition chamber, and subsequently heated at temperatures greater than 500° C. in a different chamber, such as an annealing furnace, to perform the dopant diffusion to form the doped region.
All of the above described processes for introducing dopant ions have a propensity for forming dopant ions at the surface. Depending on the device properties, the presence of dopant ions at the surface may be deleterious to device performance. Control of the dopant ions is critical to device performance because, as noted, diffusing or implanting dopant ions changes the electrical characteristics of the semiconductor material. Diffusion or implantation of the ions into undesired areas or regions can detrimentally affect device performance. For example, diffusion or implantation of arsenic dopant ions into a shallow trench isolation region can cause parasitic lateral leakage. Shallow trench isolation regions are typically fabricated into the integrated circuit to isolate neighboring devices. Leakage underneath the shallow trench isolation region from one device to another is exacerbated by the presence of dopant ions, thereby detrimentally affecting device performance. Another example of damage caused by ions implanted or diffused into undesired areas may occur during the fabrication of vertical DRAM cell array devices. In the vertical DRAM cell, the sidewalls of the isolation trench are used as the channel of the array device. The presence of dopant ions in the sidewalls, e.g., arsenic ions, would undesirably create large fluctuations on the array device threshold voltage. The noted examples are exemplary only and are used to highlight the potential problems caused by the presence of unwanted dopant ions in the semiconductor material.
Cleaning methods are frequently employed during the fabrication process to remove contaminants and residues from the wafer resulting from the various processing steps. These cleaning processes are generally aqueous based and are optimized for removing inorganic, organic and/or particulate matter. The so-called “RCA clean” has been the standard cleaning sequence utilized by the industry for cleaning silicon wafers for the past two decades. An RCA clean process comprises a multitude of steps that may be implemented in whole, or in part, at various stages during manufacture of the semiconductor circuit.
The RCA process includes a so-called “piranha” cleaning step. The piranha cleaning step typically comprises dipping the wafers in an inorganic oxidant, such as a solution containing sulfuric acid and hydrogen peroxide. This step is intended to remove organic material from a surface of the semiconductor article. A typical piranha cleaning solution would comprise hydrogen peroxide (H
2
O
2
) and sulfuric acid (H
2
SO
4
) in a ratio of about 1:5 to about 1:50 (hydrogen peroxide:sulfuric acid). The wafers are then rinsed with deionized water. The deionized water rinse typically occurs at room temperatures, commonly from about 18° C. to about 23° C. Preferably, the rinse utilizes water with a high resistivity, such as from about 10 megohms-centimeter to about 18 megohms-centimeter.
The wafers are then subjected to a so-called “HF clean”. The HF clean is typically used to remove an oxide film from the surfaces of the semiconductor wafers. Such oxide film may be formed, for example, during the above-discussed piranha clean or due to exposure of the semiconductor wafer or other article to air or other sources of oxygen, e.g., hydrogen peroxide. The HF clean typically involves dipping the wafers in a solution of water and hydrofluoric acid, with the water: hydrogen fluoride ratio commonly being in the range of from approximately 1000:1 to approximately 100:1. The wafers are then rinsed with deionized water to remove hydrogen fluoride and various materials loosened from the surface of the wafer.
The wafers may then be subjected to a so-called “Standard Clean 1” step, commonly referred to as an “SC1” step. The SC1 step is principally directed to removing various particulate materials from the semiconductor surfaces which can more easily attach as a result of the surface being made hydrophobic by the hydrogen fluoride cleaning step explained above, step 1C. In a typical SC1 step, the wafers are submerged in a solution of water, hydrogen peroxide and ammonium hydroxide (for example 5:1:1 by volume), at temperatures from about 75° C. to about 80° C. for a time of from about 2 minutes to about 15 minutes. The wafers are then rinsed with deionized water to remove the SC1 solution from the wafers.
The wafers may also be subjected to a so-called “Standard Clean 2” step, commonly referred to as an “SC2” step. The SC2 step is thought to desorb atomic and ionic contaminants from the wafers. In particular, the SC2 step is intended to remove metals deposited on the wafer surface during the HF cleaning step and SC1 step. In a typical SC2 step, the wafers are submerged in a solution of H
2
O:HCl:H
2
O
2
(for example 6:1:1 by volume). The SC2 step can be carried out at temperatures which are elevated above fabrication room temperatures. Examples of elevated temperatures sometimes used are from about 75° C. to about 80

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