Process for regeneration of a layer transferred wafer and...

Details Process for regeneration of a layer transferred wafer and... Process for regeneration of a layer transferred wafer and...

2006-12-21

2010-11-09

Le, DUng A. (Department: 2818)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S458000, C438S457000, C438S508000

Reexamination Certificate

active

07829436

ABSTRACT:
A processing time required for regeneration of a layer transferred wafer is reduced and the regeneration cost is lowered, while a removal amount at the regeneration is decreased the number of regeneration times is increased. A main surface of a semiconductor wafer (13) has a main flat portion (13d) and a chamfered portion (13c) formed in the periphery of the main flat portion (13d), an ion implanted area (13b) is formed by implanting ions only into the main flat portion (13d), a laminated body (16) is formed by laminating the main flat portion (13d) on a main surface of a support wafer (14), and moreover, the semiconductor wafer (13) is separated from a thin layer (17) in the ion implanted area (13b) by heat treatment at a predetermined temperature so as to obtain a thick layer transferred wafer (12), which is to be regenerated. The main flat portion (13d) of the semiconductor wafer (13) is formed to have a ring-shape step (13e) protruding from the chamfered portion (13c), and the semiconductor wafer (13) is separated from the thin layer (17) on the whole surface of the ion implanted area (13b) so that no step is generated in the periphery thereby to obtain the layer transferred wafer (12).

REFERENCES:
patent: 7582540 (2009-09-01), Shiota et al.
patent: 2008/0124929 (2008-05-01), Okuda et al.
patent: 2001-155978 (2001-06-01), None
patent: 02/084721 (2002-10-01), None
English Language Abstract of JP 2001-155978.
U.S. Appl. No. 11/614,792, filed Dec. 21, 2006, and entitled “Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer”.
U.S. Appl. No. 11/614,681, filed Dec. 21, 2006, and entitled “Method for Manufacturing Direct Bonded SOI Wafer and Direct Bonded SOI Wafer Manufactured by the Method.”.

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