Process for reducing waviness in semiconductor wafers

Details Process for reducing waviness in semiconductor wafers Process for reducing waviness in semiconductor wafers

1999-08-04

2001-03-13

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C216S059000, C216S084000, C438S008000, C438S009000, C438S692000, C438S753000

Reexamination Certificate

active

06200908

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a process for reducing the waviness of a semiconductor wafer. In particular, the present invention provides a process for reducing the waviness of a semiconductor wafer by selectively locally removing material from the front and/or back surface of the wafer independently from the apposing surface by plasma assisted chemical etching.
Semiconductor wafers, such as silicon wafers, are typically obtained by slicing a single crystal ingot in a direction normal to the axis of the ingot to produce thin wafers, grinding the wafers to planarize their front and back surfaces, etching the planarized wafers to remove damage created by the slicing and grinding, and polishing the etched surfaces. As a consequence of these shaping operations, the wafers may have one or more of surface roughness, waviness, or global warp. In general, surface roughness appears as jagged surface irregularities, surface waviness appears as undulatory surface irregularities having a periodicity which is generally greater than about 5 mm and less than about 30 mm (which may vary across the surface of the wafer) and an amplitude of about 0.5 &mgr;m to about 5 &mgr;m from an ideal planer surface, and global warp appears as undulatory surface irregularities having a periodicity which is generally greater than about 30 mm, and an amplitude which may be significantly greater than that exhibited by waviness. The differences between surface roughness, waviness, and global warp are schematically illustrated in FIGS.
1
(
a
) through FIG.
1
(
f
).
FIG.
1
(
a
) schematically illustrates a perfectly flat wafer in cross section wherein the front surface
1
and the back surface
2
are ideal planer surfaces, perpendicular to the axis
3
of the wafer and parallel to the median surface
4
located at the midpoint between the front surface
1
and the back surface
2
of the wafer.
FIG.
1
(
b
) schematically illustrates a wafer exhibiting waviness in cross section, wherein an ideal planer surface
5
is normal to the axis
3
of the wafer, and tangential to a valley
6
of the wave. The amplitude of the waves is equal to the distance from peak
7
adjacent to valley
6
to the ideal planer surface
5
(ie. the vertical distance from peak to valley). The wavelength is equal to the distance from any point to the next point characterized by the same phase of the wave (for example, the wavelength is equal to the distance from one peak to an adjacent peak or from one valley to the adjacent valley). Wafers exhibiting undulations having a wavelength of about 5 mm to about 30 mm and an amplitude of about 0.5 &mgr;m to about 5 &mgr;m on the surface the wafer are considered to exhibit waviness. The amplitude and wavelength may vary across the surface of the wafer.
As shown in FIG.
1
(
b
), waviness directly affects the flatness of the wafer since the distance from the front surface
1
to the ideal planer surface
5
varies across the surface of the wafer. In addition, the peaks and valleys of the front surface
1
do not necessarily align with the peaks and valleys of the back surface
2
resulting in thickness variations wherein the thickness is measured as the vertical distance from any point on the front surface
1
of the wafer to the apposing point on the back surface
2
of the wafer.
The surface of the wafer may also exhibit a degree of roughness appearing as jagged irregularities on the front surface
1
and/or back surface
2
of the wafer. FIG.
1
(
c
) schematically illustrates a wafer exhibiting roughness in cross section. In contrast to waviness, micro-roughness is characterized by a peak to peak distance of less than about 100 &mgr;m and an amplitude or vertical distance from peak to valley of less than 5 &mgr;m. In addition, saw wires leave a signature roughness on the wafer surface, which has a wavelength of 0.2 to 1.5 mm with an amplitude of about 1.0 to about 50 &mgr;m.
Typically, wafers produced by conventional wafer shaping operations may also exhibit global warp, wherein the median surface is undulatory having a periodicity which is generally greater than about 30 mm and having an amplitude that may be significantly larger than exhibited by either waviness or roughness. FIG.
1
(
d
) schematically illustrates a wafer exhibiting global warp, wherein the median surface
4
is not an ideal planer surface.
In addition to exhibiting either waviness, roughness or global warp, a wafer may exhibit any combination or all of the irregularities on the surface of the wafer. These different wavelength irregularities superimpose on each other to form a typical wafer topology after being subjected to wiresawing. For example,
FIG. 1
(
e
) schematically illustrates a wafer exhibiting both waviness and roughness in cross section and
FIG. 1
(
f
) schematically illustrates a wafer exhibiting roughness, waviness and global warp.
The flatness of a wafer is affected by roughness, waviness and global warp. Traditional shaping processes such as grinding, chemical etching and polishing are directed towards improving either the roughness or the global warp, but fail to eliminate waviness. Furthermore, wafers exhibiting only global warp may be drawn down on a vacuum chuck such that the median surface is a planer surface creating a sufficiently flat surface for device manufacturing. By removing the warp temporarily using a vacuum chuck, device manufacturers are able to process these wafers without much difficulty. The vacuum chuck will not, however, remove the waviness from the surface of the wafer. Consequently, when a wafer exhibiting waviness is drawn down to temporarily eliminate global warp, the front surface of the wafer is not sufficiently flat for device manufacturing. Thus, device manufacturers require that wafers do not exhibit waviness.
Waviness can be revealed using a “Magic Mirror” inspection tool, wherein light is reflected off of the wafer surface onto an imaging device. The imaging device produces a black and white image of the reflected light with waviness appearing as dark stripes or features in the image. Device manufacturers specify featureless wafers (ie. wafers not exhibiting waviness). Therefore, semiconductor wafers exhibiting waviness will be rejected in the final inspection which will cause yield loss.
European Patent Application No. EP 0 798405 A2 discloses a process for reducing “unevenness or swelling having cycles of 0.5 to 30 mm” on as-cut wafers right after the slicing process and before lapping, wherein a wax or like adhesive is used to hold the back surface to a chucking base plate, thus absorbing the swelling while the front surface is subsequently ground flat. In addition, EP O 798405 A2 discloses a double-sided grinding process wherein both sides of the wafer are subjected to a grinding process simultaneously to reduce the unevenness or swelling and improve the flatness of the wafers. Each of these approaches, however, relies on mechanical and/or chemomechanical processes for reducing thickness and flatness variations which leave contaminants on the surface and cause subsurface damage to the substrate.
Alternatively, EP O 798405 A2 suggests a third embodiment wherein a conventional plasma assisted chemical etching (PACE) process is used to remove stock from the surface of the wafer based on the total thickness variation to reduce unevenness or swelling and improve the flatness of semiconductor wafers. However, conventional PACE processes utilizing thickness measurements do not adequately remove waviness.
In the PACE process, a plasma generates a chemically reactive species from a gas such as sulfur hexafluoride, and the surface of the substrate facing the plasma etching electrode is etched to remove material from the surface at defined locations to improve the thickness uniformity and produce wafers with parallel apposing surfaces.
Although conventional PACE technology has many recognized advantages over other substrate thinning or flattening methods, it is not without limitations. Conventional PACE processes typically utilize a capacitanc

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