Process for reducing surface variations for polished wafer

Details Process for reducing surface variations for polished wafer Process for reducing surface variations for polished wafer

2000-02-16

2002-11-12

Goudreau, George (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C216S088000, C451S389000, C451S460000, C451S041000, C451S053000, C451S007000

Reexamination Certificate

active

06479386

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to polishing semiconductor wafers and more particularly to single side polishing semiconductor wafers to improve nanotopolgy and flatness so as to minimize thickness variations in a thin dielectric layer thickness.
The continued drive for miniaturization of electronic devices printed on semiconductor substrates places increasing technical demands on device manufacturers, and also suppliers of semiconductor wafers on which the devices are imprinted. Miniaturization is reaching the stage where circuit line widths are decreased beyond present levels, into ranges below 0.25 microns. It is well documented that decreasing the line width decreases the amount of acceptable deviations of the surface of the wafer from being perfectly flat. Semiconductor wafers, including any layers deposited on the surface of the wafer, must be particularly flat in order to print circuits on them by, for example, an electron beam-lithographic or a photolithographic process. Wafer flatness in the focal point of the electron beam delineator or optical printer is important for uniform imaging in the electron beam-lithographic and photolithographic processes. The flatness of the wafer surface directly impacts device line width capability, process latitude, yield and throughput. The depth of focus of the electron beam delineator or optical printer limits the amount of local elevational variation in the wafer surface topology which is permitted.
However it has not been as well documented, until recently, that as line widths are reduced additional problems arise related to the topology of a single (front) surface of the wafer. Devices are built up on the semiconductor substrate in numerous (e.g., 10 to 20) layers. As the line widths decrease, they become relatively tall in relation to their width. This makes it difficult to keep the built up line generally perpendicular to the wafer surface. To reduce this effect, layers are being applied with a lesser thickness. In particular, the insulating oxide (dielectric) layer has been significantly reduced in thickness. Another change to device manufacture is that it has become necessary to use chemical/mechanical planarization (CMP) on the front surface of the wafer between application of certain layers in order to maintain flatness. However, CMP decreases the thickness of the layer applied prior to CMP. Features on the surface of the wafer to which the oxide layer is applied can give rise to discontinuities in dielectric layer thickness. Where the layers are particularly thin, polishing can reduce the thickness to the point where current leakage occurs, causing failure of that part of the wafer and concomitant loss of yield.
Differences in surface elevation in the range of just 100 nanometers can cause problems with oxide layer thickness during device manufacture. One source of these discontinuities is the edge ring phenomena. Etching processes cause peripheral rings on the front and back surfaces of the wafer to form. Conventional single side polishing is not capable of removing these edge rings. Application of the oxide layer to the front surface is done with the wafer in a free state, i.e., it is not held by a vacuum chuck so that the edge ring causes the thickness of the oxide layer to be less over the edge ring than elsewhere. The thickness of the layer is further reduced when CMP is performed on the oxide layer. Because of the oxide layer is particularly thin, even a slight discontinuity in the front surface of the wafer can cause the oxide layer to be so thin after CMP that current leakage occurs and that area of the wafer fails.
In order to identify and address these problems, device and semiconductor material manufacturers are now considering the nanotopology of the front face of the wafer. Nanotopology has been defined as the deviation of a wafer surface within a spatial wavelength of about 0.2 mm to 20 mm. This spatial wavelength corresponds very closely to surface features on the nanometer scale for processed semiconductor wafers. The foregoing definition has been proposed by Semiconductor Equipment and Materials International (SEMI), a global trade association for the semiconductor industry (SEMI document 3089). Nanotopology measures on the elevational deviations of one surface of the wafer and does not consider thickness variations of the wafer, as with traditional flatness measurements. Edge rings are one of the features which most profoundly affect nanotopology, including particular oxide layer uniformity in the CMP process (see, K. V. Ravi, “Wafer Flatness Requirements for Future Technology”, Future Fab International, July, 1999). Several metrology methods have been developed to detect and record these kinds of surface variations. For instance, the measurement deviation of reflected light from incidence light allows detection of very small surface variations. These methods are used to measure peak to valley (PV) variations within the wavelength
Etching is not the only source for producing undesired surface features. Wafer producers often use identification marks on the silicon wafers to track them through the various wafering processes. In this manner, different marks can be used to indicate different wafer characteristics, identify the source of defective wafers or otherwise trace the origin of a particular wafer or lot of wafers. For example, a series of laser-scribed dots (also referred to as hard marking) may be used to form an identification number on a surface of a wafer. Lumonics sells a number of suitable dot matrix machines under the trademark WaferMark® for hard marking identification marks on silicon wafers with a laser. Laser marks on the back surfaces of wafers tend to leave corresponding bumps on the front sides of the wafers after polishing. These bumps can affect not only oxide layer thickness when the oxide layers are subjected to CMP, but also flatness.
SUMMARY OF THE INVENTION
Among the several objects and features of the present invention may be noted the provision of a process of forming semiconductor wafers which have a high degree of flatness on one side of the wafer; the provision of such a process which reduces variations in the thickness of a dielectric material on the one side of the wafer; the provision of such a process which facilitates the imprinting of extremely narrow width lines for manufacturing smaller IC devices on the wafer; the provision of such a process which reduces dielectric layer non-uniformity caused by formation of an edge ring on the wafer during prior processing of the wafer; the provision of such a process which reduces degradation in flatness and dielectric layer uniformity caused by laser marks on the back side of the wafer; the provision of such a process which reduces stress in the wafer caused by wax mounting of the wafer to a polishing block for polishing; and the provision of such a process which is readily executed using existing process equipment.
A process of forming semiconductor wafers which inhibits the formation of surface features on a polished front side of the wafer side generally comprises slicing a wafer from an ingot of semiconductor material. At least one side of the wafer is etched to remove damage. Wax in flowable form is applied to a mounting surface of the polishing block and a back side of the semiconductor wafer is pressed into the wax on the polishing block in a vacuum pressure environment to bond the wafer to the polishing block. Pressing the wafer into the wax against the polishing block moves the wafer from a relaxed configuration to a deflected configuration. The wafer as bonded to the polishing block is heated to a temperature and for a time selected to soften the wax and permit the wafer to move relative to the polishing block toward the relaxed configuration without breaking the bond of the wafer to the polishing block thereby to relieve stress in the wafer. The front side of the wafer as mounted on the polishing block by holding the polishing block and rubbing the front side of the wafer against a polishi

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