Process for reducing surface roughness of superconductor integra

Details Process for reducing surface roughness of superconductor integra Process for reducing surface roughness of superconductor integra

1998-09-18

2000-08-29

Guay, John

Etching a substrate: processes

Forming or treating josephson junction article

216 38, 505410, 505731, 505820, 427 63, C23F 100, B44C 122

Patent

active

061103926

ABSTRACT:
The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.

REFERENCES:
patent: 5477061 (1995-12-01), Morohashi
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Kerber, G. L. et al., "An Improved NbN Integrated Circuit Process Featuring Thick NbN Ground Plane and Lower Parasitic Circuir Inductances," IEEE Trans. on Applied Superconductivity, vol. 7, No. 2, Jun. 1997, pp. 2638-2643.
Kohlstedt, H. et al., "Double Barrier Long Josephson Junctions with a Contact to the Intermediate Superconducting Layer," IEEE Trans. On Applied Superconductivity, vol. 5, No. 2, Jun. 1995, pp. 2939-2942.
Marathe, Amit P. et al., "Planarization Techniques for Multilevel HTS Integrated Circuit Process," IEEE Trans. on Applied Superconductivity, vol. 3, No. 1, Mar. 1993, pp. 2373-2376.
Marathe, Amit P. et al., "Process Issues and Components for HTS Digital Integrated Circuit Fabrication," IEEE Trans. on Applied Superconductivity, vol. 5, No. 2, Jun. 1995, pp. 3135-3138.
Nagasawa, S. et al., "Nb Multilayer Planarization Technology for a Subnanosecond Josephson 1K-Bit RAM," IEEE Trans. on Magnetics, vol. 25, No. 2, Mar. 1989, pp. 777-782.
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