Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1996-10-24
1999-07-27
Dote, Janis L.
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
438626, 438633, 438697, 216 38, 216 57, 216 89, H01L 2100
Patent
active
059289600
ABSTRACT:
According to the present invention, an improved method for planarizing the surface of a dielectric or metal layer in an integrated circuit manufacturing process is disclosed. The dielectric or metal layer to be planarized is selectively patterned and etched over different regions of the surface. The size, shape, density, and depth of the patterns are determined by the pattern factor of the integrated circuit structures underlying the layer to be planarized. Further, by using the pattern factor of the underlying structures to determine the density, size, depth and placement of the surface pattern, the overall planarization process can be improved. Other empirically determined factors, such as material strength, CMP slurry temperature, and pad pressure can also be used to further refine the CMP process. By varying the pattern over the entire surface of the layer to be planarized, the CMP material removal rate can be controlled to achieve a more planar surface.
REFERENCES:
patent: 4007103 (1977-02-01), Baker et al.
patent: 5104828 (1992-04-01), Morimoto et al.
patent: 5139608 (1992-08-01), Grivna
patent: 5310626 (1994-05-01), Fernandes et al.
patent: 5328553 (1994-07-01), Poon
patent: 5332467 (1994-07-01), Sune et al.
patent: 5395801 (1995-03-01), Doan et al.
patent: 5437763 (1995-08-01), Huang
patent: 5502007 (1996-03-01), Murase
patent: 5580826 (1996-12-01), Matsubara
patent: 5663107 (1997-09-01), Peschke et al.
Greco Nancy Anne
Greco Stephen Edward
Anderson Jay
Dote Janis L.
International Business Machines - Corporation
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