Process for reducing extraneous metal plating

Stock material or miscellaneous articles – Structurally defined web or sheet – Discontinuous or differential coating – impregnation or bond

Reexamination Certificate

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Details

C174S257000, C174S250000

Reexamination Certificate

active

06455139

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method for fabricating printed circuit boards, cards and chip carriers and is especially directed to a method for plating a metal layer on the circuitized portions of an already circuitized substrate. More particularly, the method of the present invention reduces bridging that can occur during the to plating.
BACKGROUND OF INVENTION
In the manufacture of printed circuit cards and boards, a dielectric sheet material is employed as the substrate. A conductive circuit pattern is provided on one or both of the major surfaces of the substrate. The conductive pattern can be formed on the surface of the substrate using a variety of known techniques. These known techniques include the subtractive technique, where a layer of for example copper is etched to form the desired circuit pattern, the EDB (electroless direct bond) technique, where copper is electrolessly plated directly on the surface of the substrate in the desired pattern, and the peel-apart technique, where the desired circuit pattern is plated up from a thin layer of peeled-apart copper. Since the substrate employed is a dielectric, when it is desired to plate directly on the surface of the substrate, various techniques for seeding or catalyzing the substrate are used.
Furthermore, in various situations, it is desirable to selectively plate on the metallic surfaces (usually copper) as opposed to the dielectric surfaces of the substrate. This is especially true for plating copper areas that are to be used for electrical connection. For example, it is common practice to overplate copper lines with a barrier layer, typically a metal such as nickel followed by a second overplating with a precious metal such as gold, palladium or rhodium. Examples of such processes are disclosed in U.S. Pat. Nos. 4,940,181 and 5,235,139, disclosures of which are incorporated herein by reference.
However, there is a tendency for the nickel and/or precious metal to plate not only on the already present circuit lines, but also to deposit on a portion of the dielectric substrate or insulator located between lines. This problem is especially pronounced when dealing with very fine lines that are only separated by very small intervals. For example, circuit boards having surface conductive paths whose spacing is 50 microns or below have a tendency to suffer from bridging or short circuiting due to the subsequent plating of the nickel and/or precious metal. It would therefore be desirable to provide a process for plating only already circuitized lines whereby the problem of bridging is significantly reduced if not entirely eliminated.
SUMMARY OF INVENTION
The present invention is concerned with a method that significantly reduces the problem of extraneous plating in areas between circuitry on a circuitized substrate. More particularly, it has been found according to the present invention that treating an already circuitized substrate with a swelling agent and with a composition of an alkaline permanganate, a chromate or chlorite significantly reduces if not entirely eliminates the bridging problem. Accordingly, the method of the present invention relates to fabricating a printed circuit board which comprises providing a circuitized substrate and treating the circuitized substrate with a swelling agent. The substrate is then treated with a composition of an alkaline permanganate, a chromate or chlorite followed by applying a metal layer on the treated circuitized substrate to coat the circuitized portion of the substrate.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.


REFERENCES:
patent: 4812275 (1989-03-01), Yumoto
patent: 4874635 (1989-10-01), Karas et al.
patent: 4940181 (1990-07-01), Juskey, Jr. et al.
patent: 5202151 (1993-04-01), Ushio et al.
patent: 5235139 (1993-08-01), Bengston et al.
patent: 5252195 (1993-10-01), Kobayashi et al.
patent: 5468515 (1995-11-01), Ferrier et al.
patent: 5591488 (1997-01-01), Schafer et al.
patent: 5648125 (1997-07-01), Cane
patent: 5817405 (1998-10-01), Bhatt et al.

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