Process for realizing P-channel MOS transistors having a low thr

Details Process for realizing P-channel MOS transistors having a low thr Process for realizing P-channel MOS transistors having a low thr

1994-07-28

1996-07-09

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 45, 437918, H01L 218238

Patent

active

055344488

ABSTRACT:
A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,

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Davari et al., "A High Performance 0.25 .mu.m CMOS Technology", IEDM 1988.
Nygren et al., "Dual-Type CMOS Gate Electrodes by Dopant Diffusion from Silicide", IEEE Transactions on Electron Devices, vol. 36, No. 6, Jun. 1989.

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