Process for providing electrostatic discharge protection to an i

Details Process for providing electrostatic discharge protection to an i Process for providing electrostatic discharge protection to an i

1996-09-12

1998-01-13

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 51, 437 48, 437 59, H01L 2170

Patent

active

057078866

ABSTRACT:
An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.

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C. Duvvury et al., "Dynamic Gate Coupling of NMOS For Efficient Output ESD Protection," IEEE Proceedings of the IRP, Sanvary, 1992, pp. 141-150.

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