Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1985-11-15
1987-07-14
Roy, Upendra
Metal working
Method of mechanical manufacture
Assembling or joining
29576B, 29576E, 29571, 148 15, 148DIG82, 357 51, H01L 2182, H01L 21306
Patent
active
046793046
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a process for the production of zones for the electrical isolation of the components of an integrated circuit. This process can be used in the field of microelectronics whenever it is necessary to electrically isolate or insulate individual components (transistors, diodes, etc.) formed on a conductive support. It therefore more particularly applies to integrated circuits using silicon as the substrate, such as bipolar or MOS integrated circuits.
The desire to obtain a high integration density in such integrated circuits makes it necessary to use a special dielectric isolation procedure in between the different components.
At present three major groups of isolation procedures using dielectrics are known.
In the first group, the isolation between the components is effected at the surface of the integrated circuits by producing isolation zones obtained by depositing an isolating material, generally silicon oxide. This procedure has mediocre isolation performances in view of the oxide quality deposited. Moreover, it leads to the formation of high steps on the integrated circuit board at the location of the isolation zones, which is prejudicial to obtaining a high integration density.
Furthermore, in order to prevent the formation of a parasitic conductor channel beneath the isolation zones, it is necessary to locally dope the corresponding underlying regions. However, in this isolation procedure, the doping cannot be carried out with the same mask as that used for defining the isolation zones so that it is not an autopositioned procedure. Therefore, it has been virtually abandoned in connection with the production of integrated circuits using silicon as the substrate.
In the second group, the isolation between the components is obtained by means of a silicon oxide formed by the local oxidation of the silicon substrate through a mask. Prior to the oxidation of the substrate, this mask is also used for defining the zones of the substrate in which doping is carried out for eliminating the possibility of the formation of a parasitic channel beneath the oxidised region. Thus, this is in fact an autopositioned procedure.
This procedure or technology known under the term LOCOS (local oxidation) technology is at present the standard isolating procedure in integrated circuits using silicon as the substrate. However, this technology requires the formation of isolation zones with a width of 4 to 7 .mu.m, which considerably limits the integration density. Moreover, in the most recent variants of this isolation procedure, it is only possible to carry out isolation over a depth of 1 .mu.m. In addition it is only possible to obtain isolation over such a depth by carrying out high temperature thermal oxidation, which suffers from disadvantages.
In the third group, isolation between the components is obtained by opening trenches in the substrate, which are then filled with an isolating material. This filling takes place by depositing the isolating agent over the entire surface of the integrated circuit followed by removing the excess material deposited outside the trenches. The excess isolating material can be removed either by chemical or plasma etching, or by lift-off. This isolation procedure has more particularly been described in an IEDM article 1982, pp 237 to 240 entitled Deep Trench Isolated CMOS Devices.
The procedure using trenches made it possible to reach considerable isolation depths of several .mu.m, with a width not exceeding 1 micrometer. However, this procedure does not solve the key problem of the formation of parasitic channels beneath the isolation zones and on the edges of the trenches.
SUMMARY OF THE INVENTION
The present invention relates to a process for producing zones for the electrical isolation of the components of an integrated circuit making it possible to obviate the aforementioned disadvantages. This process based on the formation of trenches and local oxidation, makes it possible to prevent the formation of parasitic channels bene
REFERENCES:
patent: 3853633 (1974-12-01), Armstrong
patent: 4477310 (1984-10-01), Park et al.
patent: 4502913 (1985-03-01), Lechaton et al.
patent: 4506435 (1985-03-01), Pliskin et al.
patent: 4551911 (1985-11-01), Sasaki et al.
patent: 4584763 (1986-04-01), Jambotkar et al.
IBM Technical Disclosure Bulletin, vol. 25, No. 12, May, 1983, pp. 6611-6614, S. A. Abbas et al: "Simplified Isolation for an Integrated Circuit" *FIGS. 1-5*.
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