Process for producing wire connections on an electronic...

Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement

Reexamination Certificate

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C257S676000, C257S692000, C257S784000

Reexamination Certificate

active

06232561

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a process for producing bond wire connections and an assembly carrier made by the process.
It is known to use a process to electrically connect the electronic components such as, for example, semiconductor chips, which are assembled on an assembly carrier on board with the conductor path frame of the assembly carrier or board. In this process, the connection of the chips is accomplished in a so-called ball-wedge-bonding process in which bonded wire is connected with connection surfaces (bond surfaces) to which the conductor paths are oriented. During the ball-wedge-bonding, the wire is guided by a capillary of the bonding head. A remote first end of the wire is melted, for example, via a signal discharge device and a ball is formed due to the outer surface tension of the melted end. A weld is then formed between the electronic component connection of an electronic component on the assembly carrier and the first end of the wire via a so-called thermal welding in which pressure, heat and ultrasound effects are applied during the lowering of the capillary onto the electronic component connection. Thereafter, the capillary is moved to the connection surface of a conductor path during which movement the wire is drawn out of the capillary.
During the lowering of the capillary a second end of the wire is applied to the connection surface of the conductor path and is widened out as it is applied by the action of the capillary rim there against the wedge as well as welded to the connection surface by the action of pressure, heat, and ultrasound effects of thermal welding. The second end of the wire is created as the wire is severed from the wire supply in the capillary during the wire end application process just described. A disadvantage arises with this known process, however, in that the creation of the second thermal weld connection involving widening out of the second end of the wire requires considerably more working space than the creation of the ball on the first end of the wire as it applied to the electronic component connection. The distance between adjacent electronic component connections can on a chip, for example, amount to only 80 &mgr;m while, in contrast, the width of the connection surfaces of the conductor paths must be chosen at some multiple greater than this distance, in order to permit sufficient working room to lower the bonding tool to the connection surface. For this reason, the matrix or arrangement of the connection surfaces associated with the conductor paths is relatively much larger than the matrix or arrangement of the electronic component connections and requires much more space on the assembly carrier. Moreover, it is disadvantageous that the space between the connection surfaces of the conductor paths and the electronic component connections are not otherwise available for use since the wires extend over the space.
SUMMARY OF THE INVENTION
The present invention, in one aspect thereof, provides a process for producing the electrical connections between the connections respectively associated with the electronic components and the conductor paths, whereby the required space for the wiring of the type used in a ball-wedge-bond process is considerably reduced, in that the connection surface for each second wire end is spaced from the conductor path at a location between the electronic component matrix and the conductor path matrix and is connected to the conductor path by a second wire. The process according to the present invention advantageously permits the ball shaped type of wire end, such as is formed for the first end of the wire, to be used for both the electronic component connections as well as the connection surfaces for the conductor paths. Since the bonding tool does not require but a relatively small working space for this type of wire end bonding process, the spacing of the conductor paths from one another can be correspondingly relatively narrow, such as, for example, along the scale of the spacing between the electronic component connections to each other—namely, 80 &mgr;m. At the same time, the conductor paths can be laid more densely on the assembly carrier and the wire lengths can be thereby shortened. The second ends of each respectively paired first and second wires are welded to a common connection surface which is spaced from the conductor paths and the electronic component connections. In this way, the space between the electronic component and the conductor path matrices can be advantageously used.
The process of the present invention provides the further advantage that the shortened bonding paths reduce the wire material demand, a consequence which produces considerable savings if gold bond wire is used. Moreover, the extent of process paths on the bonding head rendered unusable as a consequence of the bond wire production is clearly reduced. Since the process of the present invention uses two wires instead of a single wire to structure an electrical connection between an electronic component and a conductor path, the wire paths are relatively flatter, whereby the mechanical stability of the bond connections is increased.
In a situation in which the space requirements for the conductor path matrix need not be limited to the least space configuration but, in contrast, the working path of the bonding tool must be constrained to the smallest possible, it is advantageous, in accordance with a further aspect of the present invention, if only every other electronic component connection is connected via two wires to the respective associated conductor path and the remaining electronic component connections are each directly connected (via a single respective wire) with their respective associated conductor path connection surfaces.
The width of the connection surface of a conductor path can be advantageously chosen to be greater than the sum of the width of the associated conductor path and the spacings of the associated conductor path to its immediately adjacent conductor paths.
It is particularly advantageous if the connection surfaces of the conductor paths, in the space between the electronic components and the ends of the conductor paths, are arranged in several rows offset with respect to one another, as in this way the available unused space between the electronic component and the conductor path matrices is particularly effectively used.


REFERENCES:
patent: 4415115 (1983-11-01), James
patent: 5124783 (1992-06-01), Sawaya
patent: 5365409 (1994-11-01), Kwon et al.
patent: 5804468 (1998-09-01), Tsuji et al.
patent: 34 47 345 A1 (1985-07-01), None
patent: 4207198 (1992-09-01), None
patent: 58-210650 (1983-12-01), None
patent: 3-167872 (1991-07-01), None
patent: 5-243306 (1993-09-01), None
Patent Abstracts of Japan Vo. 005, No. 171 (E-080), Oct. 30, 1981 & JP 56 100436 A (Toshiba Corp.), Aug. 12, 1981.
Patent Abstract of Japan vol. 004, No. 079 (E-014), Jun. 7, 1980 & JP 55 046578 A (Toshiba Corp), Jul. 11, 1985.

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