Process for producing undercut dummy gate mask profiles for MESF

Details Process for producing undercut dummy gate mask profiles for MESF Process for producing undercut dummy gate mask profiles for MESF

1987-03-30

1988-03-22

Ozaki, George T.

Fishing, trapping, and vermin destroying

437176, 156633, H01L 21265

Patent

active

047328711

ABSTRACT:
Process for producing temperature-stable undercut profiles for use in semiconductor fabrication. The process is based on the phenomenon of high etch-rate selectivity between RF- and LF- PECVD-grown silicon nitride films (12G and 13G, respectively) that are deposited on top of each other. By choosing proper film and process parameters, these PECVD nitride structures can be made stress-free: the tensile stress of the RF film (12G) compensates the compressive stress of the LF film (13G).
Also disclosed is an application of a T-shaped structure (15), produced with the new process, in a method for fabricating fully self-aligned "dummy" gate sub-micron MESFETs.

REFERENCES:
patent: 3639186 (1972-02-01), Forster et al.
patent: 4503599 (1985-03-01), Veyanagi et al.
patent: 4519127 (1985-05-01), Arai
patent: 4532004 (1985-07-01), Akiyama et al.
patent: 4561169 (1985-12-01), Miyazaki et al.
patent: 4642879 (1987-02-01), Kawata et al.
Marmillion et al., IBM Technical Disclosure Bulletin, "High Temperature Lift-Off Structure", vol. 26, No. 12, May 1984, pp. 6506 and 6507.
Lignieres et al., IBM Technical Disclosure Bulletin, "Method for Characterizing the Si.sub.3 N.sub.4 Dry Etch Process", vol. 21, No. 9, Feb. 1979, p. 3654.
Yamasaki et al., IEEE Transactions on Electron Devices, vol. ED-29, No. 11, Nov. 1982, pp. 1772-1777, "GaAs LSI-Directed MESFET's with Self-Aligned Implantation for n+-Layer Technology (SAINT)".
"Self-Align Implantation for n+ Layer Technology (SAINT) for High-Speed GaAsIcs", Electronics Letters, 4th Feb. 1982, vol. 18, No. 3, pp. 119-121.
"GaAs/(GaAl) As Heterojunction Bipolar Transistors Using a Self-Aligned Substitutional Emitter Process", IEEE Electron Device Letters, Vol. EDL-7, No. 1, Jan. 1986, pp. 8-10.
Hinkel et al., IBM Technical Disclosure Bulletin, "Method of Influencing the Etch Rate of PECVD Films and Applications of the Method", vol. 24, No. 11B, Apr. 1982, p. 6094.

Affiliated with

Also associated with

Rating

Process for producing undercut dummy gate mask profiles for MESF does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for producing undercut dummy gate mask profiles for MESF, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for producing undercut dummy gate mask profiles for MESF will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-442054