Process for producing semiconductor device

Details Process for producing semiconductor device Process for producing semiconductor device

2001-07-09

2002-12-24

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S692000, C438S697000, C438S700000

Reexamination Certificate

active

06498072

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese Patent Application No. 2000-208417 filed on Jul. 10, 2000, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for producing a semiconductor device, and more particularly, it relates to a process for producing a semiconductor device in that a uniform polishing rate can be obtained irrespective to an element region width to enable planation of an element.
2. Description of Related Art
Along with progress of fine structures of elements, an element isolating region electrically isolating elements is also demanded to miniaturize. As a method for forming a minute element isolating region, a trench isolating method has been known, in which trenches are formed on a silicon substrate, and an dielectric film (such as an oxide film) is filled in the trenches.
Examples of a process for filling the trenches with the dielectric film include an LP-CVD process, an O
3
-TEOS CVD process and an HDP-CVD (high density plasma CVD) process.
FIG. 3
is a cross sectional view of a silicon substrate having an oxide film filled therein by the LP-CVD process or the O
3
-TEOS CVD process. In the figure, numeral
31
denotes a silicon substrate,
32
denotes an oxide film, and
33
denotes an SiN film. In these processes, the isolation dimension of the trenches is decreased along with the progress of fine structures of element of the semiconductor device, and thus the filling capability of the oxide film
35
is in short in the minute trenches, so as to cause a seam
34
(gap). Owing to the presence of the seam
34
, dents are formed on the element isolating regions upon forming the semiconductor device, and a material of a gate electrode is accumulated in the dents to cause such a problem that a short circuit is formed among the gate electrodes.
In order to solve the problem, the HDP-CVD process has been widely employed. In the HDP-CVD process, an oxide film is formed, and simultaneously edges of the film thus formed are etched, so as to provide such characteristics that minute trenches can be filled.
FIG. 4
shows a cross sectional view of a silicon substrate after filling with an oxide film by the HDP-CVD process. In the figure, symbols W
1
, W
2
and W
3
denote widths of element regions, B
1
, B
2
and B
3
denote element forming regions, t denotes an accumulated thickness of an oxide film thus filled, numeral
41
denotes a silicon substrate,
42
denotes an oxide film,
43
denotes an SiN film, and
44
denotes an oxide film accumulated by the HDP-CVD process (hereinafter, referred to as an HDP-CVD oxide film). As shown in
FIG. 4
, the HDP-CVD oxide film
44
has an accumulation angle &thgr; on the element forming regions.
The element region widths W
1
and W
2
of the element forming regions B
1
and B
2
in
FIG. 4
satisfy the equation:
W
1
(
W
2
)<2
t
/tan &thgr;
and the element region width W
3
of the element forming region B
3
satisfies the equation:
W
3
>2
t
/tan &thgr;
The dielectric film accumulated on the element forming regions will be described in detail below with reference to
FIGS. 13
to
17
.
In the following description, t denotes the accumulated thickness of the dielectric film, T denotes the depth of the trench, h denotes the accumulation height of the dielectric film on the element forming region, W denotes the element region width, and &thgr; denotes the accumulation angle of the dielectric film on the element forming region.
In the case of t<T, a cross sectional view of an element forming region having an element region width W satisfying the equation:
W
≦2
t
/tan &thgr;
is shown in
FIG. 13
, and a cross sectional view of an element forming region having an element region width W satisfying the equation:
W>2
t
/tan &thgr;
is shown in FIG.
14
.
As shown in
FIG. 13
, in the case of t≧h, the dielectric film on the element forming region is in the form of an isosceles triangle having a base W and a height h=(W tan &thgr;)/2.
As shown in
FIG. 14
, in the case of t<h, the dielectric film on the element forming region is in the form of a trapezoid having a lower base W, an upper base W−(2t/tan &thgr;) and a height t.
In the case of t>T, a cross sectional view of an element forming region having an element region width W satisfying the equation:
W
≦2
t
/tan &thgr;
is shown in
FIG. 15
, and a cross sectional view of an element forming region having an element region width W satisfying the equation:
W
>2
t
/tan &thgr;
is shown in FIG.
16
.
As shown in
FIG. 15
, in the case of T≧h, the dielectric film on the element forming region is in the form of an isosceles triangle having a base W−2(t−T)/tan &thgr; and a height ((W tan &thgr;)/2)−(t−T).
As shown in
FIG. 16
, in the case of T<h, the dielectric film on the element forming region is in the form of a trapezoid having a lower base W−2(t−T)/tan &thgr;, an upper base W−2t/tan &thgr; and a height T.
A cross sectional view of an element forming region having an element region width W satisfying the equation:
W
=2
t
/tan &thgr;
is shown in FIG.
17
. In the case of t=T=h, the dielectric film on the element forming region is in the form of an isosceles triangle having a base W and a height of t=T=h.
FIGS.
5
(
a
) to
5
(
e
) show a forming process of an oxide film by the HDP-CVD process.
An oxide film
52
and an SiN film
53
are formed on a silicon substrate
51
. After coating a resist
54
, on which element isolation regions are then opened by a know photolithography technique, the SiN film
53
and the oxide film
52
are removed by anisotropic dry etching, and trenches are formed on the silicon substrate
51
(FIG.
5
(
a
)). After removing the resist
54
and subjecting the interior of the trenches to thermal oxidation, an HDP-CVD oxide film
55
is accumulated on the whole surface of the substrate (FIG.
5
(
b
)) and is polished by the CMP (chemical mechanical polishing) process until the SiN film
53
is exposed to effect planation, whereby the element isolation regions are formed (FIG.
5
(
c
)).
The planation by the CMP process is greatly affected by the element region width and the density of the element forming regions. Particularly, in the case shown in FIG.
5
(
d
) where there are both the region
1
, in which the element forming regions having the relationship between the element region width W and the accumulation thickness t of the oxide film
55
satisfying the equation W>2t/tan &thgr; are built up, and the region
2
, in which the element forming regions having the relationship between the element region width W and the accumulation thickness t of the oxide film
55
satisfying the equation W≦2t/tan &thgr; are built up, the polishing rate of the region
1
is smaller than that of the region
2
. Therefore, the period of time required for removing by polishing the oxide film
55
in the region
1
is prolonged in comparison to the polishing period required by the region
2
, and thus such a problem is developed that the oxide film in the region
2
is excessively polished when the oxide film in the region
1
is completely polished, so as to fail to obtain uniform heights after polishing (FIG.
5
(
e
)).
In order to solve the problem, JP-A-11-214499 proposes the following process to avoid the non-uniformity in polishing process. Trenches are formed on a semiconductor substrate to form element forming regions and element isolating regions, and after accumulating an HDP-CVD oxide film, a mask pattern having openings on part of the element forming regions. The oxide film on the element forming regions is once removed according to the mask pattern, planation is then carried out.
FIGS.
6
(
a
) to
6
(
e
) show a forming process of element forming region according to JP-A-11-214499.
An oxide film
62
and an SiN film
63
are formed on a silicon sub

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