Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-03-14
2003-07-15
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S638000, C438S637000, C438S713000, C438S778000
Reexamination Certificate
active
06593246
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for producing a semiconductor device, and more particularly, it relates to a process for producing a semiconductor device having a multi-layer wiring structure used for device process beyond the design rule of 0.25 &mgr;m.
2. Description of the Related Art
With the scale down of a semiconductor device, scale down of wiring and reduction of a wiring interval become necessary. Simultaneously, with the demand of low consuming electric power and high-speed operation, an inter level dielectric having a low dielectric constant and wiring having a low resistance become necessary. Particularly, in a logic device, because increase of the resistance and increase of the wiring capacitance due to the fine wiring bring about deterioration in operation speed, fine multi-layer wiring using a film having a low dielectric constant as an inter level dielectric becomes necessary.
In order to apply the dual damascene method to the inter level dielectric having a low dielectric constant, in which a conductive material is filled in a via hole and a wiring groove formed in the inter level dielectric, followed by flattening, it is necessary to employ a technique in which the via hole and the wiring groove can be simultaneously formed in the inter level dielectric having a low dielectric constant.
An organic polymer is receiving attention as the material for the inter level dielectric having a low dielectric constant. An organic polymer has a dielectric constant of about 2.7, which is lower than the conventional inter level dielectric using silicon oxide (SiO
2
) having a dielectric constant of about 4.0 and silicon oxide fluoride (SiOF) having a dielectric constant of about 3.5. Therefore, a great improvement in performance is expected in a semiconductor device using an organic polymer in an inter level dielectric. However, as the organic polymer is an expensive material, taking the balance between increase in cost and improvement in performance of the semiconductor device into consideration, it has been studied a structure, in which only the inter level dielectric having groove wiring formed therein is formed with the organic polymer, and the inter level dielectric having a via hole formed therein is formed with silicon oxide or silicon oxide fluoride, which has been conventionally used. An example of such a structure will be described below with reference to
FIGS. 1A
to
1
F.
As shown in
FIG. 1A
, a passivation film
111
comprising a material, into which a wiring material is not diffused, is formed with a silicon nitride film on a substrate
110
, in which transistors and wiring have been formed, and then a first inter level dielectric
112
, in which a via hole is to be formed, is formed with a silicon oxide film having a thickness of 500 nm. A resist mask (not shown in the figure) for forming a via hole is formed on the first inter level dielectric
112
, and a via hole
113
is formed in the first inter level dielectric
112
by etching using the resist mask as an etching mask. The resist mask is then removed.
As shown in
FIG. 1B
, a second inter level dielectric
114
, by which the via hole
113
is filled, is formed with an organic polymer having a thickness of 500 nm on the first inter level dielectric
112
.
As shown in
FIG. 1C
, a mask layer
115
to be an etching mask for forming a wiring groove is formed with a silicon oxide film having a thickness of 100 nm on the second inter level dielectric
114
. A resist mask
116
for forming a wiring groove pattern is formed on the mask layer
115
. An opening
117
for forming the wiring groove pattern is formed in the resist mask
116
.
As shown in
FIG. 1D
, the wiring groove pattern
118
is formed in the mask layer
115
by etching using the resist mask
116
as an etching mask.
As shown in
FIG. 1E
, the second inter level dielectric
114
is etched by using the resist mask
116
(see
FIG. 1D
) and the mask layer
115
as an etching mask to form a wiring groove
119
, and the second inter level dielectric
114
filled in the via hole
113
is selectively removed to re-open the via hole
113
in the first inter level dielectric
112
. Upon etching in this case, since the second inter level dielectric
114
comprising the organic polymer is etched, the resist mask
116
is simultaneously etched and removed. Therefore, a step of removing the resist mask
116
is not necessary.
Thereafter, as shown in
FIG. 1F
, the passivation film
111
exposed at the bottom of the via hole
113
is etched by using the first and second inter level dielectrics
112
and
114
as a mask. As a result, the wiring groove
119
and the via hole
113
having a dual damascene structure are formed.
The scale down of the wiring width and reduction of the interval bring about not only the aspect ratio of the wiring itself, but also the aspect ratio of the space among the wiring, and as a result, and thus difficulties are caused in the technique for forming narrow and long wiring and the technique for filling a gap among fine wiring with an inter level dielectric. Thus, the process becomes complicated, and simultaneously the number of steps contained in the process is increased.
In a damascene process, in which after a via hole and a wiring groove are simultaneously filled with an aluminum series metal or a copper series metal by reflow sputtering, an excess metal on the inter level dielectric, in which the via hole and the wiring groove are formed, is removed by chemical mechanical polishing (hereinafter referred to as CMP), it is not necessary to form metallic wiring having a high aspect ratio by etching or to fill the gap among the wiring with an inter level dielectric, and thus the number of steps of the process can be greatly reduced. This process contributes to the reduction of the total cost in a greater extent when the aspect ratio of the wiring becomes larger, or the total number of the wiring becomes larger.
An inter layer dielectric having a low dielectric constant is applied to a device of a 0.18 &mgr;m or lower design role rule since it reduces the capacitance among the wiring. A film having a specific inductive capacity of 2.5 or less has a film property that is greatly different from a silicon oxide film used in the conventional device, and thus a process technique that can be applied to the film having a low dielectric constant is demanded.
Many of the films having a low dielectric constant of 3.0 or lower are organic films containing carbon, and they are employed instead of the conventional inter level dielectric. Oxygen is necessarily used on opening a via hole in the organic film used as the inter level dielectric. However since a resist comprising an organic film is used in the patterning technique used in the conventional process for producing a semiconductor device, there is a problem in that the film having a low dielectric constant is damaged in the step of removing the resist. Because the composition of the film having a low dielectric constant is similar to the composition of the resist, there is a possibility that the film having a low dielectric constant is removed in the step of removing the resist.
In recent years, an application of xerogel to a semiconductor device is receiving attention as a material expected to have a specific inductive capacity of 2.0 or less. The xerogel is a well-known material, for example, as silica gel used as a desiccating agent. The application of xerogel to a semiconductor device is difficult at present due to a demand of various kinds of reliability. That is, xerogel contains from 50 to 90% of pores by volume and thus has a problem in mechanical strength.
In the process described with reference to
FIGS. 1A
to
1
F, the second inter level dielectric is filled in the via hole in the step shown in FIG.
1
B. Therefore, in the step shown in
FIG. 1E
, because the second inter level dielectric in the via hole is etched until it is completely removed, over etching is often applied to the bottom of the wiring groov
Hasegawa Toshiaki
Miyata Koji
Taguchi Mitsuru
Everhart Caridad
Kananen Ronald P.
Luu Chuong
Rader & Fishman & Grauer, PLLC
Sony Corporation
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