Process for producing semiconductor components between which con

Details Process for producing semiconductor components between which con Process for producing semiconductor components between which con

1995-11-03

1998-06-16

Quach, T. N.

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

438459, 438650, 438661, 438667, H01L 21283, H01L 21302

Patent

active

057670013

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a process for producing semiconductor components having a special contact structure which is provided for vertical, electrically conductive connection of a plurality of semiconductor components.
2. Description of the Related Art
Semiconductor circuits are produced nowadays using planar technology. The achievable complexity on a chip is limited by its size and the achievable fineness of the structure. The performance of a system comprising a plurality of semiconductor chips connected to one another is considerably limited in the cases of conventional technology by the limited number of possible connections between individual chips via connection contacts, the low speed of signal transfer via such connections between different chips, the limited speed in the case of complex chips due to extensively branched conductor tracks, and the high power consumption of the interface circuits.
These evinced limitations in the use of planar technology can be overcome using three-dimensional interconnection techniques. The arrangement of the functional planes above one another allows parallel communication between these components with a low requirement for electrically conductive connections in one plane, and speed-limiting interchip connections are additionally avoided.
A known process for producing three-dimensional ICs (integrated circuits) is based on depositing a further semiconductor layer over a plane of components, recrystallizing the layer using a suitable process (for example, a local heating process by means of a laser) and implementing therein a further component plane. This technique, too, has considerable limitations as a result of the thermal loading of the lower plane during recrystallization and the achievable yield which is limited by defects.
An alternative process from NEC produces the individual component planes separately from one another. These planes are thinned to a few pm and connected to one another by means of wafer bonding. The electrical connections are produced by providing: the front and rear sides of the individual component planes with contacts for interchip connection. This process has the following disadvantages and limitations; The thinned wafers must be processed on the front side and on the rear side using technical processes (lithography with adjustment by the semiconductor wafer). Testing for functionality of the individual planes prior to assembly is made more difficult by the fact that in this process individual components, but not complete circuits, are implemented in each plane. By thinning the wafers right down to the functional elements, SOI-like component structures are produced, with the result that use cannot be made of wafers which have been preproduced using standard technologies (for example standard CMOS).
It is the object of the present invention to specify a process for the simple production of semiconductor components having a contact structure suitable for three-dimensional contact-making as well as a process for the electrically conductive contact-making of a plurality of semiconductor components of this type.
This object is achieved by the process having the steps of claim 1. Further refinements emerge from the dependent claims.
In the production process according to the invention, the contact structure is produced by vertically etching out the substrate of the component, starting from the overgrown top, until there can be introduced into this pin-shaped recess a metallization layer which makes electrically conductive contact with the metal layer or semiconductor layer with which contact is to be made. The bottom of the substrate is ground back or etched back until this pin-shaped metallization layer projects beyond the substrate at the bottom. This projecting pin can be used to connect this semiconductor component in a permanently electrically conductive manner to a suitably produced contact, made of a metal having a low melting point, on the top of a further semiconductor c

REFERENCES:
patent: 4394712 (1983-07-01), Anthony
patent: 4893174 (1990-01-01), Yamada et al.
patent: 4939568 (1990-07-01), Kato et al.
patent: 5034347 (1991-07-01), Kakihana
patent: 5401672 (1995-03-01), Kurtz et al.
patent: 5447871 (1995-09-01), Goldstein
patent: 5627106 (1997-05-01), Hsu

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