Process for producing optimum intrinsic, long channel, and short

Details Process for producing optimum intrinsic, long channel, and short Process for producing optimum intrinsic, long channel, and short

1990-08-10

1992-02-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 45, 437 56, 437 57, 437 29, 148DIG82, H01L 21265

Patent

active

050913247

ABSTRACT:
Highly doped short channel NMOS devices with punch-through protection; intrinsic NMOS devices with low threshold voltage; and long channel NMOS and PMOS devices with low body factor; are constructed by providing one or more lightly doped P regions in a semiconductor wafer in which intrinsic and long channel NMOS devices may be constructed, and one or more N wells in the wafer where PMOS devices can be constructed; forming isolation oxide on the wafer before implanting the wafer to inhibit field inversion in N channel (NMOS) devices; masking N regions of the wafer except where long channel PMOS devices will be formed and portions of P regions of the wafer where long channel NMOS devices will be constructed, and optionally masking P regions where either intrinsic NMOS devices or short channel NMOS devices will be formed; and then implanting the wafer to simultaneously provide a field implant below the isolation oxide, adjacent regions where NMOS devices will be formed, as well as optionally providing a deep implant in P regions where short channel NMOS devices will be constructed to provide punchthrough protection, and optionally providing a deep implant in P regions where intrinsic NMOS devices will be constructed to raise the threshold voltage of such intrinsic devices; then masking P regions of the wafer where intrinsic NMOS devices will be constructed; and implanting the wafer to provide a V.sub.T adjustment to optimize threshold voltages of long channel and short channel NMOS and PMOS devices.

REFERENCES:
patent: 4435895 (1984-03-01), Parrillo et al.
patent: 4530150 (1985-07-01), Shirato
patent: 4845047 (1989-07-01), Holloway et al.
patent: 4889825 (1989-12-01), Parrillo
patent: 4943537 (1990-07-01), Harrington, III
patent: 5024961 (1991-06-01), Lee et al.

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