Process for producing multi-level metallization in an integrated

Details Process for producing multi-level metallization in an integrated Process for producing multi-level metallization in an integrated

1997-03-27

1999-09-21

Niebling, John F.

Semiconductor device manufacturing: process

Dummy metallization

438183, 438626, 438631, 438599, 438645, 438691, 438942, H01L 21027, H01L 21304

Patent

active

059566183

ABSTRACT:
A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

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S. Wolf, "Silicon Processing for the VLSI Era, vol. 1", Lattice Press, 1986, pp. 476-482.

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