Process for producing minimal geometry devices for VSLI applicat

Details Process for producing minimal geometry devices for VSLI applicat Process for producing minimal geometry devices for VSLI applicat

1978-06-06

1980-10-28

Tupman, W. C.

29571, 29577C, 29589, 357 41, 357 59, H01L 2978

Patent

active

042310512

ABSTRACT:
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for diffused conducting lines in the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having oxidation and etch characteristics permits selective oxidation of desired portions only of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. There results semiconductor devices of minimum geometry with selective interconnection capabilities, affording VLSI circuits having increased density with improved yield and reliability.

REFERENCES:
patent: 4080719 (1978-03-01), Wilting
patent: 4102733 (1978-07-01), De La Moneda

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