Process for producing memory cell having stacked capacitor

Details Process for producing memory cell having stacked capacitor Process for producing memory cell having stacked capacitor

1986-12-01

1988-05-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 52, 437919, 357 236, 357 71, 148DIG14, 365149, H01L 2170, H01L 2700

Patent

active

047420189

ABSTRACT:
A process for producing a memory cell having a stacked capacitor. As the reduction in device size of memory cells progresses, it becomes difficult to obtain a satisfactorily large capacitance even with a stacked capacitor structure. To enable a larger capacitance to be obtained for the same occupied area, projections and recesses are provided on the surface of a capacitor electrode. It is possible, according to the process, to readily produce projections and recesses for increasing the storage capacitance.

REFERENCES:
patent: 4355374 (1982-10-01), Sakai et al.
Koyanagi, et al., "Novel High Density, Stacked Capacitor MOS RAM," IEDM Technical Digest, 1978, pp. 348-351.
Koyanagi et al., "Novel High Density, Stacked Capacitor MOS RAM," Japanese Journal of Applied Physics, vol. 18, 1979, Supplement 18-1, pp. 35-42.

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