Process for producing high-epsilon dielectric layer or...

Details Process for producing high-epsilon dielectric layer or... Process for producing high-epsilon dielectric layer or...

1999-03-30

2002-02-12

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000

Reexamination Certificate

active

06346424

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates in general to the field of semiconductors, and specifically to a process for producing a high-e dielectric layer or a ferroelectric layer on a substrate, that is used in particular for producing an integrated semiconductor memory.
In the production of integrated circuits, high-e dielectric materials and ferroelectric materials are gaining increasing importance. They are used, for example, as the capacitor dielectric in integrated circuit memories. Because of their high dielectric constant (∈
r
of a few hundred), less space is needed for the storage capacitor, and because of the different polarization directions in the ferroelectric material it is possible to construct a non volatile memory called a FRAM. In a FRAM, no information is lost if the voltage supply is interrupted and no continuous refresh is required.
Examples of such materials include barium strontium titanate (BST), strontium titanate (ST), lead zirconium titanate (PZT), SBT (SrBi
2
Ta
2
O
9
), and SBTN (SrBi
2
Ta
2
-xNbxO
9
). These materials are produced by a sputtering, spin-on or deposition process which requires high temperatures (≧700° C.) in an atmosphere containing oxygen. When used in a storage cell, which for example is constructed as a stacked capacitor, a noble metal such as platinum or ruthenium is used as the material for the first electrode since conductive materials, such as polysilicon or aluminum, that are customarily used as an electrode material oxidize under these conditions. Electrodes containing noble metals are, however, permeable to oxygen with the result that, during the production of the capacitor dielectric, deep structures become oxidized and satisfactory electrical contact between the first electrode and the selection transistor of the storage cell is not guaranteed. Prior art structures require a barrier below the capacitor dielectric that prevents oxygen from diffusing. However, these diffusion barriers can also oxidize during production of the capacitor dielectric causing the electrical connection between the first electrode and the selection transistor to be broken. In addition to the high temperature, a major cause of the oxidation is the long duration (up to 60 min) of the deposition or heat treatment.
The article by A. Yuuki et al., IEDM 95, Technical Digest, page 115, discloses a process in which the crystallization of a BST film produced in a CVD process is carried out by heat treatment in N
2
. However, a layer produced by this process has high leakage currents.
The article by C. S. Hwang et al., Appl. Phys. Lett. 67 (1995), page 2819, describes the heat treatment of sputtered BST layers at 550° C. to 750° C. in nitrogen and oxygen. The process is not, however, suitable for the production of a storage cell since the heat treatment at these temperatures in oxygen oxidizes the barrier to such an extent that the electrical connection to the selection transistor is broken.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a process for producing a high-∈ dielectric layer or a ferroelectric layer using lower levels of heating.
With the foregoing and other objects in view there is provided, in accordance with the invention, a process for producing a layer on a substrate, which comprises:
selecting a layer from the group consisting of a high-e dielectric layer and a ferroelectric layer;
sputtering the layer onto a substrate at a first temperature below 500° C.;
performing an RTP step in an inert atmosphere at a second temperature in a range from 500° C. to 900° C.; and
heat treating the layer in an atmosphere containing oxygen at a third temperature in a range from 200° C. to 600° C.
In accordance with an added feature of the invention, the second temperature is in a range from 600° C. to 800° C.
In accordance with an additional feature of the invention, the RTP step is performed in an atmosphere including nitrogen.
In accordance with an another feature of the invention, the the third temperature is in a range from 300° C. to 500° C.
In accordance with a further feature of the invention, the RTP step is performed in an atmosphere consisting of nitrogen.
In accordance with a further added feature of the invention, the heat treating step is performed for a duration of 1 to 15 minutes.
In accordance with a further additional feature of the invention, before performing the sputtering step, an integrated circuit memory cell is provided.
With the objects of the invention in view, there is also provided a process for producing a layer on a substrate which comprises:
selecting a layer from the group consisting of a high-e dielectric layer and a ferroelectric layer;
sputtering the layer onto a substrate at a first temperature below 500° C.;
performing an RTP step in an inert atmosphere at a second temperature in a range from 500° C. to 900° C.; and
heat treating the layer in an atmosphere selected from the group consisting of oxygen and air, at a third temperature in a range of 200° C. to 600° C. for a duration of 1 to 15 minutes.
In the invention, a multistage procedure having at least three steps is used in order to prevent oxidation of the barrier. In the first step, the layer is sputtered at a low substrate temperature (T
1
<500° C.). However, the layer obtained in this way is not crystalline or has a very small grain size. This results in a very low ∈. The second step is an RTP step (Rapid Thermal Processing) at a medium to a high temperature (T
2
: 500 to 900° C., preferably 600 to 800° C.) in an inert atmosphere that does not contain any oxygen. A nitrogen atmosphere, Ar or an Ar/N
2
mixture are particularly suitable. The N
2
atmosphere prevents oxidation of the barrier since all of the oxygen is bound in the layer. After this step, the layer has a high ∈, but nevertheless has high leakage currents that are attributable to oxygen vacancies in the layer. In the third step, a heat after-treatment is carried out at a low or a medium temperature (T
3
: 200 to 600° C., preferably 300 to 500° C.) in an atmosphere containing oxygen. During this step, oxygen is added to the layer and the leakage currents are reduced by several orders of magnitude. Performance of this step causes ∈ to decrease only slightly. The duration of the heat after-treatment may be up to 1 hour, but is typically 1 to 15 min. To prevent oxidation of the barrier, the temperature of this procedural step should not be too high.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a process for producing a high-e dielectric layer or ferroelectric layer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


REFERENCES:
patent: 5063422 (1991-11-01), Hillenius et al.
patent: 5099305 (1992-03-01), Takenaka
patent: 5943568 (1999-08-01), Fujii et al.
patent: 0 380 326 (1990-08-01), None
patent: 2-208937 (1990-08-01), None
Stanley Wolf Ph.D. and Richard N. Tauber Ph.D. in Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986, p. 57.*
“Deposition of extremely thin (Ba, Sr) TiO3thin films for ultra-large-scale integrated dynamic random access memory application” (Hwang et al.), 320 Applied Physics Letters, vol. 67, No. 19, New York 1995, pp. 2819-2821.
“Novel Stacked Capacitor Technology for 1 Gbit DRAMs with CVD-(Ba, Sr) TiO3thin films on a thick, storage node of Ru” (Yuuki et al.), IEDM 95, Technical Digest, pp. 115-118.
“Quasi-Epitaxial Growth of PZT thin film to fabricate capa

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