Fishing – trapping – and vermin destroying
Patent
1994-06-13
1995-07-04
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437193, 437200, 437245, 437 50, H01L 2144
Patent
active
054299888
ABSTRACT:
A process of fabricating a semiconductor device on a substrate with closely spaced high density conductive lines is provided. A thin insulating layer is formed on the surface of a substrate. Next, a blanket conductive layer and a blanket masking layer are deposited over the first insulating layer. Using conventional photolithography processes and plasma etching, elongated spaced parallel masking lines with vertical sidewalls are formed in the masking layer. A blanket polycrystalline silicon layer is deposited on the masking lines and the exposed areas of the conductive layer. Next, the blanket polycrystalline silicon layer is anisotrophically etched to form spacers on the vertical sidewalls of the masking lines. A second planarized masking layer is formed over the spacers and masking lines. The polycrystalline silicon spacers and the underlying first polycrystalline silicon layer are anisotrophically etched to form the closely spaced conductive lines in the first polycrystalline silicon layer. A coating of electrically isolating material is formed between and over the conductive lines.
REFERENCES:
patent: 4502914 (1985-03-01), Trumpp et al.
patent: 4776922 (1988-10-01), Bhattacharyya et al.
patent: 5236853 (1993-08-01), Hsue
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patent: 5328810 (1994-07-01), Lowrey et al.
patent: 5330924 (1994-07-01), Huang et al.
Chen Kun-Luh
Huang Heng Sheng
Wu Wood
Chaudhuri Olik
Everhart C.
Saile George O.
United Microelectronics Corporation
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